7.3.3 Reference Voltage Range for G=1/4 (INA151D)

The topology of the internal amplifiers in INA151D establishes constraint on linear performance dependent on

supply voltage, common-mode input voltage and reference voltage. Figure 7-6 illustrates this interdependency,

showing how the (input referred) offset voltage increases non-linearly if the reference voltage exceeds the linear

operating range.

For a power supply configuration of VS= ±5V and common-mode input voltage set to mid-supply, VREF must stay

at or below GND (down to negative supply, thus −5V) for linear operating range.

For a power supply configuration of VS = ±10V and common-mode input voltage set to mid-supply, VREF must

stay at or below 2V (down to negative supply, thus −10V) for linear operating range.

Figure 7-6. Offset Voltage (RTI) vs Reference Voltage of INA151D

7.4 Device Functional Modes

The INA151 has two functional modes of operation being enabled when the enable pin is driven to logic

high and being disabled when the enable pin is driven logic low and the output stage being shut off. When

the device is enabled, the device draws a typical consumption current of 450μA. When disabled the current

consumption is 30% lower at typical 300μA. The device is functional as long as the power supply voltages are

in the recommended operating voltage range of 2.7V (±1.35V) to 20V (±10V). Operational temperature range of

INA151 is from –40°C to 125°C.

7.4.1 Output Enable and Disable

The INA151 includes an enable pin (EN) that enables or disables the output stage of the amplifier. When the

output stage is disabled, the output is set to a high-impedance state.

This function can be leveraged to perform a multiplexing function in a stacked system with multiple channels,

eliminating the need for an external multiplexer. By sequentially enabling one device at a time while keeping

other devices disabled, each output can be directly sampled by a single ADC input. Additionally the disable

function achieves a 30% reduction of quiescent current, thereby supporting power efficient operation in power

sensitive applications.

When the enable pin is driven to logic high (EN=HIGH), the device needs to bias internally with a typical delay

time of 15μs until settled to 0.1% error band. When disabled the device shut down within a delay of 16μs

(typical). Consider implementing enough delay time between disabling one channel and enabling the subsequent

channel.

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INA151

SLVSIL6B – JANUARY 2026 – REVISED MARCH 2026

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