8.4 Layout

8.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

the following PCB layout practices:

• Verify that both input paths are well-matched for source impedance and capacitance to avoid converting

common-mode signals into differential signals.

• Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

– Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Route the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than crossing

in parallel with the noisy trace.

• Place the external components as close to the device as possible.

• Keep the traces as short as possible.

8.4.2 Layout Example

8

VS+

INN

7

OUT

INP

6

EN

4

VS

5

REF

1

2

3

GND

+IN

–IN

GND

GPIO

C2

C1

Place bypass

capacitors as close to

IC as possible

V

C1

R1

R2

C5

C4

C3

DGND

VOUT

+

DGND

GND

C1

C2

VS+

VS

EN

R1

R2

IN

+IN

C5

C4

C3

OUT

REF

REF

GND

Figure 8-6. Example Schematic and Associated PCB Layout

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INA151

SLVSIL6B – JANUARY 2026 – REVISED MARCH 2026

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