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TLK1002A

DUAL SIGNAL CONDITIONING TRANSCEIVER

SLLS661 – JUNE 2005

TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

NO.

NAME

1

RXA–

In

Inverted data input A. On board AC coupled. On-chip 100-

Ω differential terminated to RXA+.

2

RXA+

In

Non-inverted data input A. On board AC coupled. On-chip 100-

Ω differential terminated to RXA–.

3, 4, 7, 12, 15,

GND

Supply

Circuit ground. The exposed die pad (EP) must be grounded.

16,19, 24, EP

5

TXA+

VML-out

Retimed non-inverted data output A. On board AC coupled.

6

TXA–

VML-out

Retimed inverted data output A. On board AC coupled.

8

RCLK

CMOS-in

Reference clock input. Self biased for AC coupling. This input is 2.5 V tolerant.

Enable A, on-chip pulled up to VDD. When set to high level, the VML output buffer driving the

9

ENA

CMOS-in

TXA+/TXA– port is enabled. This input is 2.5 V tolerant.

Enable B, on-chip pulled up to VDD. When set to high level, the VML output buffer driving the

10

ENB

CMOS-in

TXB+/TXB– port is enabled. This input is 2.5 V tolerant

11, 20, 23

VDD

Supply

1.8 V ±5% supply voltage

13

TXB–

VML-out

Retimed inverted data output B. On board AC coupled.

14

TXB+

VML-out

Retimed non-inverted data output B. On board AC coupled.

17

RXB+

In

Non-inverted data input B. On board AC coupled. On-chip 100-

Ω differential terminated to RXB–.

18

RXB–

In

Inverted data input B. On board AC coupled. On-chip 100-

Ω differential terminated to RXB+.

Loop back B, on-chip pulled up to VDD. When pulled to low level, loop back mode B is enabled

21

LBB

CMOS-in

The input data applied to the input port RXB+/RXB– is retimed and fed to both output ports

TXA+/TXA– and TXB+/TXB–. This input is 2.5 V tolerant.

Loop back A, on-chip pulled up to VDD. When pulled to low level, loop back mode A is enabled

22

LBA

CMOS-in

The input data applied to the input port RXA+/RXA– is retimed and fed to both output ports

TXB+/TXB– and TXA+/TXA–. This input is 2.5 V tolerant.

4