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Y1

−Y1

0

Y2

−Y2

X1

0

1−X1

1

Y1

−Y1

0

Y2

−Y2

X2

0

1−X2

1

X1

1−X1

OPERATIONAL MODES

NORMAL OPERATION MODE

TLK1002A

DUAL SIGNAL CONDITIONING TRANSCEIVER

SLLS661 – JUNE 2005

AC ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE CLOCK AC SPECIFICATIONS

Reference clock low level voltage

DC coupled

–0.3

0.3

V

Reference clock high level voltage

DC coupled

1.5

2.1

V

Reference clock swing

AC coupled

1.2

2.4

Reference clock input threshold (self biasing)

AC coupled

0.9

V

Clock duty cycle

40%

60%

Rise / fall time

20% to 80%

300

1500

ps

Baud/10

Up to 10 MHz

40

80

∆f

RCLK

Frequency difference between reference clock

Reference clock and incoming data

–200

200

ppm

and incoming data signal

are off the nominal data rate but in

opposite direction

(3)

Reference clock is not locked to the data frequency and may deviate by

∆ f

(4)

as to reduced jitter tolerance.

Figure 2. Input Eye Mask

Figure 3. Output Eye Mask

In normal operation, the data signal at the RXA+/RXA– pins is applied to an input buffer stage, which drives a

signal conditioning PLL. The retimed output signal is connected to the output pins TXB+/TXB– by means of a

multiplexer stage and a VML output buffer.

On the other side, the input signal applied to the RXB+/RXB– pins is connected to a signal conditioning PLL by

means of an input buffer stage. The retimed output signal of the PLL is connected to the output pins TXA+/TXA–

using a multiplexer stage as well as a VML output driver.

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