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+

−

input buffer

stage

VML output

buffer

Q

Q

input buffer

stage

+

-

VML output

buffer

Q

Q

MUX

I1

I2

Q

SEL

reference voltage and

bias current generation

VDD

GND

VDD

GND

RXB+

RXB−

TXA+

TXA−

RXA+

RXA−

TXB+

TXB−

RCLK

low−noise

half−rate clock

synthesizer PLL

ICLK

RCLK

QCLK

signal

conditioning PLL

ICLK

DOUT

DIN

QCLK

signal

conditioning PLL

ICLK

DIN

DOUT

QCLK

2

2

2

amplifier

stage

2

MUX

I1

I2

Q

SEL

2

LBB

ENB

ENA

LBA

2

2

2

2

INTERNAL LOOP-BACK MODES A AND B

+

−

input buffer

stage

VML output

buffer

Q

Q

input buffer

stage

+

-

VML output

buffer

Q

Q

MUX

I1

I2

Q

SEL

reference voltage and

bias current generation

VDD

GND

VDD

GND

RXB+

RXB−

TXA+

TXA−

RXA+

RXA−

TXB+

TXB−

RCLK

low−noise

half−rate clock

synthesizer PLL

ICLK

RCLK

QCLK

signal

conditioning PLL

ICLK

DOUT

DIN

QCLK

signal

conditioning PLL

ICLK

DIN

DOUT

QCLK

2

2

2

amplifier

stage

2

MUX

I1

I2

Q

SEL

2

LBB

ENB

ENA

LBA

2

2

2

2

TLK1002A

DUAL SIGNAL CONDITIONING TRANSCEIVER

SLLS661 – JUNE 2005

OPERATIONAL MODES (continued)

The signals applied to the RXA+/RXA– input is not fed to any output in this mode.

Figure 6. Data Path in Internal Loop-Back Mode B

If both internal loop-back modes A and B are activated simultaneously, by pulling the LBA and the LBB pins low,

the input data signal at RXA+/RXA– is applied to an input buffer driving a signal conditioning PLL. The retimed

output signal is fed to the output TXA+/TXA– by means of a multiplexer stage and a VML output buffer.

The signals applied to the RXB+/RXB– input drives an input buffer connected to a signal conditioning PLL. The

retimed output signal is connected to the output pins TXB+/TXB– by means of a multiplexer stage and a VML

output buffer.

Figure 7. Data Path in Internal Loop-Back Modes A and B

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