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+

−

input buffer

stage

VML output

buffer

Q

Q

input buffer

stage

+

-

VML output

buffer

Q

Q

MUX

I1

I2

Q

SEL

reference voltage and

bias current generation

VDD

GND

VDD

GND

RXB+

RXB−

TXA+

TXA−

RXA+

RXA−

TXB+

TXB−

RCLK

low−noise

half−rate clock

synthesizer PLL

ICLK

RCLK

QCLK

signal

conditioning PLL

ICLK

DOUT

DIN

QCLK

signal

conditioning PLL

ICLK

DIN

DOUT

QCLK

2

2

2

amplifier

stage

2

MUX

I1

I2

Q

SEL

2

LBB

ENB

ENA

LBA

2

2

2

2

INTERNAL LOOP-BACK MODE A

+

−

input buffer

stage

VML output

buffer

Q

Q

input buffer

stage

+

-

VML output

buffer

Q

Q

MUX

I1

I2

Q

SEL

reference voltage and

bias current generation

VDD

GND

VDD

GND

RXB+

RXB−

TXA+

TXA−

RXA+

RXA−

TXB+

TXB−

RCLK

low−noise

half−rate clock

synthesizer PLL

ICLK

RCLK

QCLK

signal

conditioning PLL

ICLK

DOUT

DIN

QCLK

signal

conditioning PLL

ICLK

DIN

DOUT

QCLK

2

2

2

amplifier

stage

2

MUX

I1

I2

Q

SEL

2

LBB

ENB

ENA

LBA

2

2

2

2

INTERNAL LOOP-BACK MODE B

TLK1002A

DUAL SIGNAL CONDITIONING TRANSCEIVER

SLLS661 – JUNE 2005

OPERATIONAL MODES (continued)

Figure 4. Data Path in Normal Operation Mode

In internal loop-back mode A operation, which is activated by pulling the LBA pin to logic low level, the input data

signal at the RXA+/RXA– pins is applied to the input buffer driving a signal conditioning PLL. The retimed output

signal is connected to the output pins TXB+/TXB– by means of a multiplexer stage and a VML output buffer.

Furthermore, by means of a second multiplexer the same signal is fed to the second VML output buffer, which

drives the TXA+/TXA– output.

The signal applied to the RXB+/RXB– input is not fed to any output in this mode.

Figure 5. Data Path in Internal Loop-Back Mode A

In internal loop-back mode B operation, which is activated by pulling the LBB pin low, the input data signal at the

RXB+/RXB–

 pins is applied to an input buffer driving a signal conditioning PLL. The retimed output signal is

connected to the output pins TXA+/TXA– by means of a multiplexer stage and a VML output buffer.

Additionally, by means of a second multiplexer, the same signal is fed to the second VML output buffer, which

drives the TXB+/TXB– output

8