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DC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

TLK1002A

DUAL SIGNAL CONDITIONING TRANSCEIVER

SLLS661 – JUNE 2005

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply voltage

1.7

1.8

1.9

V

Current from 1.8 V supply

ENA = high, ENB = high,

158

mA

Low level CMOS input voltage

–0.2

0.6

V

High level CMOS input voltage

2.7

V

Low level CMOS input current

–120

µA

High level CMOS input current

165

µA

20

k

Ω

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DATA PATHS

Differential input impedance

100

Ω

Total input jitter

BER

0.606

UI

Deterministic input jitter

BER

0.373

Common-mode input voltage

1200

mV

Single-ended input voltage swing

200

800

1200

Differential input voltage swing

400

1600

2400

BER

0.303

UI

See Figure 2

Input eye mask

200

mV

1200

mV

Output signal rise/fall time

20% to 80%

150

260

ps

Total output jitter

1.25 Gbps input from 3.3G pattern

0.20

0.28

UI

generator at 0 ppm

Deterministic output jitter

1.25 Gbps input from 3.3G pattern

0.1

generator at 0 ppm

Common-mode output voltage

800

1000

1200

mV

Single-ended output voltage swing

440

800

1000

Differential output voltage

880

1600

2000

0.12

UI

1.25 Gbps input from 3.3G pattern

0.32

UI

Output eye mask

generator at 0 ppm

440

mV

See Figure 3

1000

mV

RX to TX latency

25

ns

Lock acquisition from link down

4

µs

Lock recovery on link discontinuity

1.6

µs

(1)

Assuming maximum initial CDR phase offset and maximum frequency difference between reference clock and input data.

(2)

The output data may contain bit errors during lock-in time, dependent on the input-data sequence and the input-data jitter. However it is

assured, that the output-data does not contain bits with widths deviating significantly from the nominal bit width.

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