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MPD78C10AL Datasheet(PDF) 15 Page - NEC |
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MPD78C10AL Datasheet(HTML) 15 Page - NEC |
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15 / 373 page  – viii – LIST OF FIGURES (2/3) Figure No. Title Page 6-24 Timer/Event Counter Mode Register Setting (Single Pulse Output: CO0 Output Timing Setting) ....................................................................................................................... 103 6-25 Interrupt Mask Register (MKL) Setting (Single Pulse Output: INTE1 Mask Release) ........... 104 7-1 Serial Interface Configuration ................................................................................................ 107 7-2 Serial Mode High Register (SMH) Format ............................................................................. 111 7-3 Serial Mode Low Register (SML) Format .............................................................................. 113 7-4 Serial Mode Register Format in Asynchronous Mode ........................................................... 115 7-5 Asynchronous Data Format ................................................................................................... 118 7-6 Serial Mode Register Format in Synchronous Mode ............................................................. 121 7-7 Synchronous Mode Timing .................................................................................................... 122 7-8 Serial Mode Register Format in I/O Interface Mode .............................................................. 123 7-9 I/O Interface Mode Timing ..................................................................................................... 124 7-10 Example of Serial Data Transfer System Configuration ......................................................... 127 7-11 Serial Mode Register Setting ................................................................................................. 128 7-12 Timer Mode Register Setting ................................................................................................ 129 7-13 Port C Setting (Serial Interface) ............................................................................................. 130 7-14 Serial Mode High Register (SMH) Setting (Serial Interface: Transmission Enable) .............. 130 7-15 Interrupt Mask Register (MKH) Setting (Serial Interface: INTSR Mask Release) ................. 133 7-16 Serial Mode High Register (SMH) Setting (Serial Interface: Reception Enable) ................... 133 8-1 A/D Converter Block Diagram ................................................................................................ 138 8-2 A/D Channel Mode Register Format ..................................................................................... 141 8-3 A/D Channel Mode Register in Scan Mode ........................................................................... 142 8-4 Outline of A/D Converter Operation Timing in Scan Mode .................................................... 143 8-5 A/D Channel Mode Register in Select Mode ......................................................................... 143 8-6 Outline of A/D Converter Operation Timing in Select Mode ................................................. 144 8-7 Relationship Between Analog Input Voltage and A/D Conversion Results ............................ 145 8-8 Memory Map (Store Example of A/D Conversion Result) ..................................................... 146 8-9 A/D Channel Mode Register Settings .................................................................................... 147 9-1 Interrupt Control Circuit Block Diagram ................................................................................. 154 9-2 Mask Register (MKL, MKH) Format ...................................................................................... 156 9-3 Interrupt Sampling ................................................................................................................. 159 9-4 Interrupt Operation Procedure ............................................................................................... 161 9-5 Internal Configuration of NMI Pin .......................................................................................... 162 9-6 Interrupt Servicing Sequence (Masking released for both INT1 and INT2) ............................ 164 9-7 Interrupt Servicing Sequence (Masking released for either INT1 or INT2) ............................ 165 9-8 3-Level Multiple Interrupts ..................................................................................................... 169 10-1 HALT Mode Release Timing (RESET Signal Input) ................................................................ 172 10-2 HALT Mode Release Timing (In EI State) .............................................................................. 173 10-3 HALT Mode Release Timing (In DI State) .............................................................................. 173 10-4 Software STOP Mode Release Timing (RESET Signal Input) ................................................ 175 10-5 SB Flag Operation .................................................................................................................. 176 10-6 Software STOP Mode Release Timing (NMI Signal Input) .................................................... 176 10-7 Hardware STOP Mode Release Timing (STOP Signal Input) ................................................. 178 10-8 Hardware STOP Mode Release Timing (RESET Signal Input) ............................................... 178 10-9 Hardware STOP Mode Release Timing (STOP Signal Rising to RESET Signal Input) ........... 179 10-10 Relation between VDD and SB Flag ........................................................................................ 179 10-11 Oscillator Connection Circuit ................................................................................................. 182 10-12 Example of External Clock Input Circuit ................................................................................. 182 10-13 Examples of Poor Resonator Connection Circuit ................................................................... 183 |
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