16-Bit DACs with 32-Channel

Sample-and-Hold Outputs

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11

rising edge of SCLK after

CS goes low will clock in the

MSB of the input word.

When each serial word is complete, the value is stored

in the SRAM at the address indicated and the control

bits are saved. Note that data may be corrupted if

CS is

not held low for an integer multiple of 24 bits.

All of the digital inputs include Schmitt-trigger buffers to

accept slow-transition interfaces. Their switching

threshold is compatible with TTL and most CMOS logic

levels.

Serial Input Data Format and

Control Codes

The 24-bit serial input format, shown in Figure 4, compris-

es of 16 data bits (D15–D0), five address bits (A4–A0),

two control bits (C1, C0), and a fill zero. The address

code selects the output channel as shown in Table 2. The

control code configures the device as follows:

1) If C1 = 1, Immediate Update Mode is selected.

If C1 = 0, Burst Mode is selected.

2) If C0 = 0, the internal sequencer clock is selected. If

C0 = 1, the external sequencer clock is selected.

This must be repeated with each data word to main-

tain external input.

A4

A3

A2

A1

A0

OUTPUT

00000

OUT0 selected

00001

OUT1 selected

00010

OUT2 selected

00011

OUT3 selected

00100

OUT4 selected

00101

OUT5 selected

00110

OUT6 selected

00111

OUT7 selected

01000

OUT8 selected

01001

OUT9 selected

01010

OUT10 selected

01011

OUT11 selected

01100

OUT12 selected

01101

OUT13 selected

01110

OUT14 selected

01111

OUT15 selected

10000

OUT16 selected

10001

OUT17 selected

10010

OUT18 selected

10011

OUT19 selected

10100

OUT20 selected

10101

OUT21 selected

10110

OUT22 selected

10111

OUT23 selected

11000

OUT24 selected

11001

OUT25 selected

11010

OUT26 selected

11011

OUT27 selected

11100

OUT28 selected

11101

OUT29 selected

11110

OUT30 selected

11111

OUT31 selected

Table 2. Channel/Output Selection