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DAC39RF10 Datasheet(PDF) 224 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 224 Page - Texas Instruments |
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224 / 232 page ![]() Layer14 / PWR4 DAC VDDR = RED DAC VDDSYS18 = GREEN DAC VDDCLK18 = BLUE VDDIO = WHITE Figure 9-32. Power Plane Layout for Layer 14 In addition, TI recommends the following general PCB fabrication considerations for all high-speed PCB designs: 1. Use high quality dielectric materials for any critical signal layers within the PCB stack-up. Typically, the top and bottom layers are the most critical and more board houses can implement a mix of high and standard quality dielectrics, also known as a hybrid stack-up. 2. Use multiple power layers if necessary to provide a robust power delivery system to the converter. 3. Use multiple ground, power, ground layer stacks within the PCB to develop high frequency decoupling within the PCB, the recommendation for these layers is 4 mils or less. 4. Use a solid ground plane, do not split or “slot” the ground plane to create an analog versus digital grounding barrier or divider to avoid harm. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 224 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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