DRA752ABC datasheet(207/443 Pages) TI2

207 / 443 page

vinx_clki

SPRS8xx_VIP_01

207

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

www.ti.com

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

7.6

Video Input Ports (VIP)

The Device includes 3 Video Input Ports (VIP).

Table 7-3, Figure 7-4 and Figure 7-5 present timings and switching characteristics of the VIPs.

CAUTION

The IO timings provided in this section are applicable for all combinations of

signals for vin1, vin5 and vin6. However, the timings are only valid for vin2,

vin3, and vin4 if signals within a single IOSET are used. The IOSETs are

defined in the Table 7-4, Table 7-5 and Table 7-6.

Table 7-3. Timing Requirements for VIP (1)(2)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, vinx_clki (3) (5)

6.06 (1)

tw(CLKH)

Pulse duration, vinx_clki high (3) (5)

0.45*P (2)

tw(CLKL)

Pulse duration, vinx_clki low (3) (5)

0.45*P (2)

tsu(CTL/DATA-CLK)

Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,

vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3)

(4) (5)

vin1x,

vin2x

2.93

vin5x,

vin6x

3.11

vin3x,

vin4x

3.11

th(CLK-CTL/DATA)

Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi,

vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition

(3) (4) (5)

-0.05

(1) For maximum frequency of 165 MHZ.

(2) P = vinx_clki period.

(3) x in vinx = 1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b, 5a and 6a.

(4) n in dn = 0 to 7 when x = 1b, 2b, 3b and 4b;

n = 0 to 15 when x = 5a and 6a;

n = 0 to 23 when x = 1a, 2a, 3a and 4a;

(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.

Figure 7-4. Video Input Ports clock signal

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