DRA752ABC datasheet(204/443 Pages) TI2

204 / 443 page

= V

MAX (or V

MAX)

ref

= V

MIN (or V

MIN)

ref

pm_transvolt_prs403

204

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Timing Requirements and Switching Characteristics

Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels

7.3.1.2

1.8V and 3.3V Signal Transition Rates

The default SLEWCONTROL settings in each pad configuration register must be used to ensure timings,

unless specific instructions otherwise are given in the individual timing sub-sections of the datasheet.

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

7.3.1.3

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routes. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information

specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to

attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis

application report (literature number SPRA839). If needed, external logic hardware such as buffers may be

used to compensate any timing differences.

7.4

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input

transitions are more susceptible to glitches due to noise and special care should be taken for slow input

clocks.

7.5

Virtual and Manual I/O Timing Modes

Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing

Modes. Table 7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device

interfaces. The individual interface timing sections found later in this document provide the full description

of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the

TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.

Table 7-2. Modes Summary

Virtual or Manual IO Mode Name

Data Manual Timing Mode

VIP

VIP1_MANUAL1

VIN1A/1B/2A Rise-Edge Capture Mode Timings

VIP1_2B_MANUAL1

VIN2B Rise-Edge Capture Mode Timings

VIP1_MANUAL2

VIN1A/1B/2A Fall-Edge Capture Mode Timings

VIP1_2B_MANUAL2

VIN2B Fall-Edge Capture Mode Timings

VIP2_MANUAL1

VIN3A, VIN3B IOSET1 Rise-Edge Capture Mode Timings

VIP2_4A_MANUAL1

VIN4A IOSET1/2 Rise-Edge Capture Mode Timings

VIP2_4A_IOSET3_MANUAL1

VIN4A IOSET3 Rise-Edge Capture Mode Timings

VIP2_4B_MANUAL1

VIN4B Rise-Edge Capture Mode Timings

VIP2_3B_IOSET2_MANUAL1

VIN3B IOSET2 Rise-Edge Capture Mode Timings

VIP2_3B_IOSET2_MANUAL2

VIN3B IOSET2 Fall-Edge Capture Mode Timings

VIP2_MANUAL2

VIN3A, VIN3B IOSET1, VIN4A IOSET1/2 Fall-Edge Capture Mode Timings

VIP2_4A_MANUAL2

VIN4A IOSET1/2 Fall-Edge Capture Mode Timings

VIP2_4A_IOSET3_MANUAL2

VIN4A IOSET3 Fall-Edge Capture Mode Timings

DRA752ABC Datasheet(PDF) 204 Page - Texas Instruments

DRA752ABC Datasheet(HTML) 204 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL