DRA752ABC datasheet(203/443 Pages) TI2

203 / 443 page

ref

pm_io_volt_prs403

Transmission Line

4.0 pF

1.85 pF

Z0 = 50

(see Note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be

taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is

intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

42 Ω

3.5 nH

Device Pin

(see Note)

pm_tstcirc_prs403

203

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

www.ti.com

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Timing Requirements and Switching Characteristics

Table 7-1. Timing Parameters (continued)

SUBSCRIPTS

SYMBOL

PARAMETER

Active Edge

First Edge

Last Edge

High impedance

7.3.1

Parameter Information

Figure 7-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals.

This load capacitance value does not indicate the maximum load the device is capable of driving.

7.3.1.1

1.8V and 3.3V Signal Transition Levels

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD

I/O)/2.

Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL

MAX and VOH MIN for output clocks.

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