DRA752ABC datasheet(200/443 Pages) TI2

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DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Clock Specifications

Table 6-13. DPLL Type A Characteristics (continued)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

prelock-F

Relock time—Phase lock(5)

(fast relock time from bypass)

3.55 + 120 ×

REFCLK

µs

DPLL in fast relock time:

lowcurrstdby = 0

(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.

For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.

(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.

(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down

by factor of M3.

(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.

(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.

(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.

Table 6-14. DPLL Type B Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

finput

CLKINP input clock frequency

0.62

MHz

FINP

finternal

REFCLK internal reference

clock frequency

0.62

2.5

MHz

[1 / (N + 1)] × FINP

fCLKINPULOW

CLKINPULOW bypass input

clock frequency

0.001

600

MHz

Bypass mode: fCLKOUT =

fCLKINPULOW / (M1 + 1) If

ulowclken = 1(4)

fCLKLDOOUT

CLKOUTLDO output clock

frequency

20(1)(5)

2500(2)(5)

MHz

M / (N + 1)] × FINP × [1 / M2]

(in locked condition)

fCLKOUT

CLKOUT output clock

frequency

20(1)(5)

1450(2)(5)

MHz

[M / (N + 1)] × FINP × [1 / M2]

(in locked condition)

fCLKDCOLDO

Internal oscillator (DCO) output

clock frequency

750(5)

1500(5)

MHz

[M / (N + 1)] × FINP (in locked

condition)

1250(5)

2500(5)

MHz

CLKOUTLDO period jitter

–2.5%

2.5%

The period jitter at the output

clocks is ± 2.5% peak to peak

CLKOUT period jitter

CLKDCOLDO period jitter

tlock

Frequency lock time

350 ×

REFCLKs

µs

plock

Phase lock time

500 ×

REFCLKs

µs

trelock-L

Relock time—Frequency lock(3)

(LP relock time from bypass)

9 + 30 ×

REFCLKs

µs

prelock-L

Relock time—Phase lock(3) (LP

relock time from bypass)

9 + 125 ×

REFCLKs

µs

(1) The minimum frequency on CLKOUT is assuming M2 = 1.

For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.

(2) The maximum frequency on CLKOUT is assuming M2 = 1.

(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.

(4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM.

(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.

6.3.2

DLL Characteristics

Table 6-15 summarizes the DLL characteristics and assumes testing over recommended operating

conditions.

Table 6-15. DLL Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

finput

Input clock frequency (EMIF_DLL_FCLK)

266

MHz

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