DRA752ABC datasheet(197/443 Pages) TI2

197 / 443 page

rtc_osc_xi_clkin32

CK0

CK1

197

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

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SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Clock Specifications

Table 6-11. RTC Oscillator Input Clock Electrical Characteristics—Bypass Mode

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

CK0

1/tc(rtc_osc_xi_clkin32) Frequency, rtc_osc_xi_clkin32

32.768

kHz

CK1

tw(rtc_osc_xi_clkin32)

Pulse duration, rtc_osc_xi_clkin32 low or

high

0.45 *

tc(rtc_osc_xi_clkin32)

0.55 *

tc(rtc_osc_xi_clkin32)

CIN

Input capacitance

2.178

2.378

2.578

IIN

Input current (3.3V mode)

µA

tsX

Start-up time

See (1)

(1) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is

inapplication mode and receives a wave. The switching time in this case is about 100 μs.

Figure 6-13. rtc_osc_xi_clkin32 Input Clock

6.2

RC On-die Oscillator Clock

NOTE

The OSC_32K_CLK clock, provided by the On-die 32K RC oscillator, inside of the SoC, is

not accurate 32kHz clock.

The frequency may significantly vary with temperature and silicon characteristics.

For more information about OSC_32K_CLK see the Device TRM, Chapter: Power, Reset, and Clock

Management.

6.3

DPLLs, DLLs Specifications

NOTE

For more information, see:

•

Power, Reset and Clock Management / Clock Management Functional / Internal Clock

Sources / Generators / Generic DPLL Overview Section

and

•

Display Subsystem / Display Subsystem Overview section of the Device TRM.

To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the

PRCM module. They are of two types: type A and type B DPLLs.

•

They have their own independent power domain (each one embeds its own switch and can be

controlled as an independent functional power domain)

•

They are fed with ALWAYS ON system clock, with independent control per DPLL.

The different DPLLs managed by the PRCM are listed below:

•

DPLL_MPU: It supplies the MPU subsystem clocking internally.

•

DPLL_IVA: It feeds the IVA subsystem clocking.

•

DPLL_CORE: It supplies all interface clocks and also few module functional clocks.

•

DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a

96-MHz functional clock to subsystems and peripherals.

•

DPLL_ABE: It provides clocks to various modules within the device.

•

DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).

•

DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).

•

DPLL_EVE: It provides the Embedded Vision Engine Subsystem (EVE1/2/3/4) clocking.

DRA752ABC Datasheet(PDF) 197 Page - Texas Instruments

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