DRA752ABC datasheet(199/443 Pages) TI2

199 / 443 page

199

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

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SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Clock Specifications

Table 6-12. DPLL Control Type (continued)

DPLL NAME

TYPE

CONTROLLED BY PRCM

DPLL_DEBUGSS

Table 6-13 (Type A)

No(2)

DPLL_DSP

Table 6-13 (Type A)

Yes(1)

DPLL_EVE

Table 6-13 (Type A)

Yes(1)

DPLL_GMAC

Table 6-13 (Type A)

Yes(1)

DPLL_HDMI

Table 6-14 (Type B)

No(2)

DPLL_IVA

Table 6-13 (Type A)

Yes(1)

DPLL_MPU

Table 6-13 (Type A)

Yes(1)

DPLL_PER

Table 6-13 (Type A)

Yes(1)

APLL_PCIE

Table 6-13 (Type A)

Yes(1)

DPLL_PCIE_REF

Table 6-14 (Type B)

Yes(1)

DPLL_SATA

Table 6-14 (Type B)

No(2)

DPLL_USB

Table 6-14 (Type B)

Yes(1)

DPLL_USB_OTG_SS

Table 6-14 (Type B)

No(2)

DPLL_VIDEO1

Table 6-13 (Type A)

No(2)

DPLL_VIDEO2

Table 6-13 (Type A)

No(2)

DPLL_DDR

Table 6-13 (Type A)

Yes(1)

DPLL_GPU

Table 6-13 (Type A)

Yes(1)

(1) DPLL is in the always-on domain.

(2) DPLL is not controlled by the PRCM.

Table 6-13 and Table 6-14 summarize the DPLL characteristics and assume testing over recommended

operating conditions.

Table 6-13. DPLL Type A Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

finput

CLKINP input frequency

0.032

MHz

FINP

finternal

Internal reference frequency

0.15

MHz

REFCLK

fCLKINPHIF

CLKINPHIF input frequency

1400

MHz

FINPHIF

fCLKINPULOW

CLKINPULOW input frequency

0.001

600

MHz

Bypass mode: fCLKOUT =

fCLKINPULOW / (M1 + 1) if

ulowclken = 1(6)

fCLKOUT

CLKOUT output frequency

20(1)

1800(2)

MHz

[M / (N + 1)] × FINP × [1 / M2]

(in locked condition)

fCLKOUTx2

CLKOUTx2 output frequency

40(1)

2200(2)

MHz

2 × [M / (N + 1)] × FINP × [1 /

M2] (in locked condition)

fCLKOUTHIF

CLKOUTHIF output frequency

20(3)

1400(4)

MHz

FINPHIF / M3 if clkinphifsel = 1

40(3)

2200(4)

MHz

2 × [M / (N + 1)] × FINP × [1 /

M3] if clkinphifsel = 0

fCLKDCOLDO

DCOCLKLDO output

frequency

2800

MHz

2 × [M / (N + 1)] × FINP (in

locked condition)

tlock

Frequency lock time

6 + 350 ×

REFCLK

µs

plock

Phase lock time

6 + 500 ×

REFCLK

µs

trelock-L

Relock time—Frequency

lock(5) (LP relock time from

bypass)

6 + 70 ×

REFCLK

µs

DPLL in LP relock time:

lowcurrstdby = 1

prelock-L

Relock time—Phase lock(5)

(LP relock time from bypass)

6 + 120 ×

REFCLK

µs

DPLL in LP relock time:

lowcurrstdby = 1

trelock-F

Relock time—Frequency

lock(5) (fast relock time from

bypass)

3.55 + 70 ×

REFCLK

µs

DPLL in fast relock time:

lowcurrstdby = 0

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