DRA752ABC datasheet(193/443 Pages) TI2

193 / 443 page

CL=

C C

(C +C )

193

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

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SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Clock Specifications

NOTE

The load capacitors, Cf1 and Cf2 in Figure 6-6, should be chosen such that the below

equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All

discrete components used to implement the oscillator circuit should be placed as close as

possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.

Figure 6-7. Load Capacitance Equation

The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-5 summarizes

the required electrical constraints.

Table 6-5. OSC1 Crystal Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Parallel resonance crystal frequency

Range from 19.2 to 32

MHz

Cf1

Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2

Cf2

Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2

ESR(Cf1,Cf2)

Crystal ESR

100

Crystal shunt capacitance

ESR = 30 Ω

19.2 MHz

≤fp≤32 MHz

ESR = 40 Ω

19.2 MHz

≤fp≤32 MHz

ESR = 50 Ω

19.2 MHz

≤fp≤25 MHz

25 MHz<fp≤27 MHz

27 MHz<fp≤32 MHz

Not Supported

ESR = 60 Ω

19.2 MHz

≤fp≤23 MHz

23 MHz<fp≤25 MHz

25 MHz<fp≤32 MHz

Not Supported

ESR = 80 Ω

19.2 MHz

≤fp≤23 MHz

23 MHz

≤fp≤25 MHz

25 MHz<fp≤32 MHz

Not Supported

ESR = 100 Ω

19.2 MHz

≤fp≤20 MHz

20 MHz<fp≤32 MHz

Not Supported

Crystal motional inductance for fp = 20 MHz

10.16

Crystal motional capacitance

3.42

tj(xiosc1)

Frequency accuracy(1), xi_osc1

Ethernet and MLB not

used

±200

ppm

Ethernet RGMII and

RMII using derived

clock

±50

Ethernet MII using

derived clock

±100

MLB using derived

clock

±50

(1) Crystal characteristics should account for tolerance+stability+aging.

When selecting a crystal, the system design must take into account the temperature and aging

characteristics of a crystal versus the user environment and expected lifetime of the system.

Table 6-6 details the switching characteristics of the oscillator and the requirements of the input clock.

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