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DRA752ABC Datasheet(PDF) 121 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 443 page  121 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 www.ti.com SPRS950F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated NOTE In the DRA74x device, the PCIe_SS2 controller is NOT available, and the PCIe_SS1 controller supports only a single lane. The PCIe2_PHY interface signal set (pcie_rxn1/rxp1, pcie_txn1/txp1 in Table 4-18) is NOT supported in the DRA74x device. For more details on the device differentiation, refer to the Table 3-1, Device Comparison. Table 4-18. PCIe Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL pcie_rxn0 PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only. IOS AG13 pcie_rxp0 PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only. IOS AH13 pcie_txn0 PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only. ODS AG14 pcie_txp0 PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only. ODS AH14 pcie_rxn1(1) PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IOS AG11 pcie_rxp1(1) PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IOS AH11 pcie_txn1(1) PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AG12 pcie_txp1(1) PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AH12 ljcb_clkp PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (positive) IODS AG15 ljcb_clkn PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (negative) IODS AH15 (1) This is not applicable for DRA74x devices. 4.4.16 Controller Area Network Interface (DCAN) NOTE For more information, see the Serial Communication Interface / DCAN section of the device TRM. Table 4-19. DCAN Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL DCAN 1 dcan1_tx DCAN1 transmit data pin IO G20 dcan1_rx DCAN1 receive data pin IO G19 / AD17 DCAN 2 dcan2_tx DCAN2 transmit data pin IO E21/ B21 dcan2_rx DCAN2 receive data pin IO F20/ AC17/ B20 4.4.17 Ethernet Interface (GMAC_SW) CAUTION The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the Table 7-75, Table 7-78, Table 7-83 and Table 7-90. |
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