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DRA752ABC Datasheet(PDF) 119 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 119 Page - Texas Instruments |
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119 / 443 page  119 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 www.ti.com SPRS950F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-15. McASP Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL mcasp7_axr3 McASP7 Transmit/Receive Data IO J14 mcasp7_ahclkx McASP7 Transmit High-Frequency Master Clock O B26 mcasp7_aclkx(1) McASP7 Transmit Bit Clock IO G14 mcasp7_fsx McASP7 Transmit Frame Sync IO F14 mcasp7_aclkr(1) McASP7 Receive Bit Clock IO G14 mcasp7_fsr McASP7 Receive Frame Sync IO F14 Multichannel Audio Serial Port 8 mcasp8_axr0 McASP8 Transmit/Receive Data IO D15 mcasp8_axr1 McASP8 Transmit/Receive Data IO B16 mcasp8_axr2 McASP8 Transmit/Receive Data IO E15 mcasp8_axr3 McASP8 Transmit/Receive Data IO A20 mcasp8_ahclkx McASP8 Transmit High-Frequency Master Clock O C23 mcasp8_aclkx(1) McASP8 Transmit Bit Clock IO B17 mcasp8_fsx McASP8 Transmit Frame Sync IO A17 mcasp8_aclkr(1) McASP8 Receive Bit Clock IO B17 mcasp8_fsr McASP8 Receive Frame Sync IO A17 (1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any non-monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS. 4.4.13 Universal Serial Bus (USB) NOTE For more information, see: Serial Communication Interface / SuperSpeed USB DRD Subsystem section of the device TRM. Table 4-16. Universal Serial Bus Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL Universal Serial Bus 1 usb1_dp USB1 USB2.0 differential signal pair (positive) IO AD12 usb1_dm USB1 USB2.0 differential signal pair (negative) IO AC12 usb1_drvvbus USB1 Drive VBUS signal O AB10 usb_rxn0 USB1 USB3.0 receiver negative lane I AF12 usb_rxp0 USB1 USB3.0 receiver positive lane I AE12 usb_txn0 USB1 USB3.0 transmitter negative lane O AC11 usb_txp0 USB1 USB3.0 transmitter positive lane O AD11 Universal Serial Bus 2 usb2_dp USB2 USB2.0 differential signal pair (positive) IO AE11 usb2_dm USB2 USB2.0 differential signal pair (negative) IO AF11 usb2_drvvbus USB2 Drive VBUS signal O AC10 Universal Serial Bus 3 usb3_ulpi_d0 USB3 - ULPI 8-bit data bus IO AC3 / AE1 usb3_ulpi_d1 USB3 - ULPI 8-bit data bus IO AC9 / AE5 usb3_ulpi_d2 USB3 - ULPI 8-bit data bus IO AC6 / AE3 usb3_ulpi_d3 USB3 - ULPI 8-bit data bus IO AC7 / AF1 usb3_ulpi_d4 USB3 - ULPI 8-bit data bus IO AC4 / AF4 usb3_ulpi_d5 USB3 - ULPI 8-bit data bus IO AD4 / AF3 usb3_ulpi_d6 USB3 - ULPI 8-bit data bus IO AB4 / AF6 |
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