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DRA752ABC Datasheet(PDF) 116 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 116 Page - Texas Instruments |
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116 / 443 page  116 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-13. SPI Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL spi3_d0 SPI3 Data. Can be configured as either MISO or MOSI. IO AE9/ W9/ C11/ B13/ AC6/ G16 spi3_cs0 SPI3 Chip Select IO AF8/ V9/ D11/ A12/ AC9/ D17 spi3_cs1 SPI3 Chip Select IO B11/ AC3/ E14 spi3_cs2 SPI3 Chip Select IO F11 spi3_cs3 SPI3 Chip Select IO A10 Serial Peripheral Interface 4 spi4_sclk(1) SPI4 Clock IO N7/ G1/ AA3/ V7/ AC8 spi4_d1 SPI4 Data. Can be configured as either MISO or MOSI. IO R4/ G6/ AB9/ U7/ AD6 spi4_d0 SPI4 Data. Can be configured as either MISO or MOSI. IO N9/ F2/ AB3/ V6/ AB8 spi4_cs0 SPI4 Chip Select IO P9/ F3/ AA4/ U6/ AB5 spi4_cs1 SPI4 Chip Select IO P4 / Y1 spi4_cs2 SPI4 Chip Select IO R3 / W9 spi4_cs3 SPI4 Chip Select IO T2 / V9 (1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any non-monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS. 4.4.11 Quad Serial Peripheral Interface (QSPI) NOTE For more information see the Serial Communication Interface / Quad Serial Peripheral Interface section of the device TRM. Table 4-14. QSPI Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL qspi1_sclk QSPI1 Serial Clock O R2 qspi1_rtclk QSPI1 Return Clock Input.Must be connected from QSPI1_SCLK on PCB. Refer to PCB Guidelines for QSPI1 I R3 qspi1_d0 QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read and quad read modes it becomes input data pin during read phase. IO U1 qspi1_d1 QSPI1 Data[1]. Input read data in all modes I P3 qspi1_d2 QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during read phase I U2 qspi1_d3 QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during read phase I T2 qspi1_cs0 QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes O P2 qspi1_cs1 QSPI1 Chip Select[1] O P1 qspi1_cs2 QSPI1 Chip Select[2] O T7 qspi1_cs3 QSPI1 Chip Select[3] O P6 |
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