DRA752ABC datasheet(112/443 Pages) TI2

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DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Terminal Configuration and Functions

Table 4-8. GPMC Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

BALL

gpmc_cs5

GPMC Chip Select 5 (active low)

gpmc_cs6

GPMC Chip Select 6 (active low)

gpmc_cs7

GPMC Chip Select 7 (active low)

gpmc_clk(1)(2)

GPMC Clock output

gpmc_advn_ale

GPMC address valid active low or address latch enable

gpmc_oen_ren

GPMC output enable active low or read enable

gpmc_wen

GPMC write enable active low

gpmc_ben0

GPMC lower-byte enable active low

gpmc_ben1

GPMC upper-byte enable active low

gpmc_wait0

GPMC external indication of wait 0

gpmc_wait1

GPMC external indication of wait 1

P7 / N1

(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the

clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.

(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the

associated timing. See Table 7-26 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 7-28

GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.

(3) The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 1 as described in

the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should

be set to 0. If gpmc boot mode is used with SYSBOOT15=1 (not recommended) then external pull-downs should be implemented to

keep the address bus at logic-0 value during boot since the gpmc ms-address bits are high-z during boot.

4.4.6

Timers

NOTE

For more information, see the Timers section of the device TRM.

Table 4-9. Timers Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

timer1