DRA752ABC datasheet(110/443 Pages) TI2

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DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Terminal Configuration and Functions

Table 4-7. EMIF Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

BALL

ddr2_dqs3

Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the

EMIF2 memory when writing and input when reading.

M28

ddr2_dqsn3

Data strobe 3 invert

M27

ddr2_vref0

Reference Power Supply EMIF2

N22

(1) The ECC module (EMIF1 ECC Data Bus in Table 4-4) signal sets are NOT supported in the DRA74x device. For more details on the

device differentiation, refer to the Table 3-1, Device Comparison.

4.4.5

General-Purpose Memory Controller (GPMC)

NOTE

For more information, see the Memory Subsystem / General-Purpose Memory Controller

section of the device TRM.

Table 4-8. GPMC Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

gpmc_ad0

GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1

in A/D multiplexed mode

gpmc_ad1

GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2

in A/D multiplexed mode

gpmc_ad2

GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3

in A/D multiplexed mode

gpmc_ad3

GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4

in A/D multiplexed mode

gpmc_ad4

GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5

in A/D multiplexed mode

gpmc_ad5

GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6

in A/D multiplexed mode

gpmc_ad6

GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7

in A/D multiplexed mode

gpmc_ad7

GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8

in A/D multiplexed mode

gpmc_ad8

GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9

in A/D multiplexed mode

gpmc_ad9

GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10

in A/D multiplexed mode

gpmc_ad10

GPMC Data 10 in A/D nonmultiplexed mode and additionally Address

11 in A/D multiplexed mode

gpmc_ad11

GPMC Data 11 in A/D nonmultiplexed mode and additionally Address

12 in A/D multiplexed mode

gpmc_ad12

GPMC Data 12 in A/D nonmultiplexed mode and additionally Address

13 in A/D multiplexed mode

gpmc_ad13

GPMC Data 13 in A/D nonmultiplexed mode and additionally Address

14 in A/D multiplexed mode

gpmc_ad14

GPMC Data 14 in A/D nonmultiplexed mode and additionally Address

15 in A/D multiplexed mode

gpmc_ad15

GPMC Data 15 in A/D nonmultiplexed mode and additionally Address

16 in A/D multiplexed mode

gpmc_a0

GPMC Address 0. Only used to effectively address 8-bit data

nonmultiplexed memories

R6 / P4

gpmc_a1

GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D

multiplexed mode

T9 / P1

gpmc_a2

GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D

multiplexed mode

T6 / N1

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