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DRA752ABC Datasheet(PDF) 106 Page - Texas Instruments

Part # DRA752ABC
Description  DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0
PDF  443 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DRA752ABC Datasheet(HTML) 106 Page - Texas Instruments

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106
DRA756, DRA755, DRA754, DRA752
DRA751, DRA750, DRA746, DRA745, DRA744
SPRS950F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744
Terminal Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Table 4-6. HDMI Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
hdmi1_hpd
HDMI display hot plug detect
I
B21/ G20
hdmi1_ddc_scl
HDMI display data channel clock
IOD
C25
hdmi1_ddc_sda
HDMI display data channel data
IOD
F17
hdmi1_clockx
HDMI clock differential positive or negative
ODS
AG16
hdmi1_clocky
HDMI clock differential positive or negative
ODS
AH16
hdmi1_data2x
HDMI data 2 differential positive or negative
ODS
AG19
hdmi1_data2y
HDMI data 2 differential positive or negative
ODS
AH19
hdmi1_data1x
HDMI data 1 differential positive or negative
ODS
AG18
hdmi1_data1y
HDMI data 1 differential positive or negative
ODS
AH18
hdmi1_data0x
HDMI data 0 differential positive or negative
ODS
AG17
hdmi1_data0y
HDMI data 0 differential positive or negative
ODS
AH17
4.4.4
External Memory Interface (EMIF)
NOTE
For more information, see the Memory Subsystem / EMIF Controller section of the device
TRM.
NOTE
The index numbers 1 and 2 which are part of the EMIF1 and EMIF2 signal prefixes (ddr1_*
and ddr2_*) listed in Table 4-7, EMIF Signal Descriptions, not to be confused with DDR1 and
DDR2 types of SDRAM memories.
Table 4-7. EMIF Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
EMIF Channel 1
ddr1_csn0
EMIF1 Chip Select 0
O
AH23
ddr1_cke
EMIF1 Clock Enable
O
AG22
ddr1_ck
EMIF1 Clock
O
AG24
ddr1_nck
EMIF1 Negative Clock
O
AH24
ddr1_odt0
EMIF1 On-Die Termination for Chip Select 0
O
AE20
ddr1_casn
EMIF1 Column Address Strobe
O
AC18
ddr1_rasn
EMIF1 Row Address Strobe
O
AF20
ddr1_wen
EMIF1 Write Enable
O
AH21
ddr1_rst
EMIF1 Reset output (DDR3-SDRAM only)
O
AG21
ddr1_ba0
EMIF1 Bank Address
O
AF17
ddr1_ba1
EMIF1 Bank Address
O
AE18
ddr1_ba2
EMIF1 Bank Address
O
AB18
ddr1_a0
EMIF1 Address Bus
O
AD20
ddr1_a1
EMIF1 Address Bus
O
AC19
ddr1_a2
EMIF1 Address Bus
O
AC20
ddr1_a3
EMIF1 Address Bus
O
AB19
ddr1_a4
EMIF1 Address Bus
O
AF21
ddr1_a5
EMIF1 Address Bus
O
AH22
ddr1_a6
EMIF1 Address Bus
O
AG23
ddr1_a7
EMIF1 Address Bus
O
AE21



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