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DRA752ABC Datasheet(PDF) 108 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 108 Page - Texas Instruments |
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108 / 443 page  108 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-7. EMIF Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL ddr1_ecc_d7 EMIF1 ECC Data Bus (1) IO Y26 ddr1_dqm0 EMIF1 Data Mask O AD23 ddr1_dqm1 EMIF1 Data Mask O AB23 ddr1_dqm2 EMIF1 Data Mask O AC26 ddr1_dqm3 EMIF1 Data Mask O AA27 ddr1_dqm_ecc EMIF1 ECC Data Mask O V26 ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AH25 ddr1_dqsn0 Data strobe 0 invert IO AG25 ddr1_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AE27 ddr1_dqsn1 Data strobe 1 invert IO AE28 ddr1_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AD27 ddr1_dqsn2 Data strobe 2 invert IO AD28 ddr1_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO Y28 ddr1_dqsn3 Data strobe 3 invert IO Y27 ddr1_dqs_ecc EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading. IO V27 ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe IO V28 ddr1_vref0 Reference Power Supply EMIF1 A Y18 EMIF Channel 2 ddr2_csn0 EMIF2 Chip Select 0 O P24 ddr2_cke EMIF2 Clock Enable O U24 ddr2_ck EMIF2 Clock O T28 ddr2_nck EMIF2 Negative Clock O T27 ddr2_odt0 EMIF2 On-Die Termination for Chip Select 0 O R23 ddr2_casn EMIF2 Column Address Strobe O U28 ddr2_rasn EMIF2 Row Address Strobe O T23 ddr2_wen EMIF2 Write Enable O U25 ddr2_rst EMIF2 Reset output (DDR3-SDRAM only) O R24 ddr2_ba0 EMIF2 Bank Address O U23 ddr2_ba1 EMIF2 Bank Address O U27 ddr2_ba2 EMIF2 Bank Address O U26 ddr2_a0 EMIF2 Address Bus O R25 ddr2_a1 EMIF2 Address Bus O R26 ddr2_a2 EMIF2 Address Bus O R28 ddr2_a3 EMIF2 Address Bus O R27 ddr2_a4 EMIF2 Address Bus O P23 ddr2_a5 EMIF2 Address Bus O P22 ddr2_a6 EMIF2 Address Bus O P25 ddr2_a7 EMIF2 Address Bus O N20 ddr2_a8 EMIF2 Address Bus O P27 ddr2_a9 EMIF2 Address Bus O N27 ddr2_a10 EMIF2 Address Bus O N23 ddr2_a11 EMIF2 Address Bus O P26 ddr2_a12 EMIF2 Address Bus O N28 ddr2_a13 EMIF2 Address Bus O T22 |
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