RH850 datasheet(32/422 Pages) RENESAS

32 / 422 page

RH850/F1KH, RH850/F1KM

Section 1C Overview of RH850/F1KM-S1

R01DS0442EJ0100 Rev.1.00

Page 32 of 422

Sep 15, 2023

Note 1.

The trace RAM is only supported by products with 1 MB code flash memory.

Figure 1C.2

Internal Block Diagram (RH850/F1KM-S1 64-Pin Version)

P-Bus

System control

LVI

Peripheral

Group 1

Peripheral

Group 2

Peripheral

Group 3

Flash interface

System interconnect

DMA

(16 ch)

OSTM

(1 unit)

CSIH

(1 ch)

CSIG

(1 ch)

RS-CANFD

(3 ch)

WDTA

(2 units)

TAUD

(1 unit)

TAUJ

(4 units)

RTCA

(1 unit)

ENCA

(1 unit)

Motor

control

PWM-Diag

(24 ch)

INTC2

DMA reg

Data flash

(64 KB)

ADCA0

RLIN3

(2 ch)

RLIN2

(2 ch)

RIIC

(2 ch)

(8 ch)

Flash

controller

DCRA

(1 ch)

Port

RSENT

(2 ch)

ICUSE

CLMA

(3 ch)

LVI

MainOSC

LS IntOSC

HS IntOSC

PLL1

STBC

CVM

POC

LPS

Code flash

(1 MB (max.))

Local RAM

(96 KB (max.))

Trace RAM*1

(32 KB)

Debug

Retention RAM

(32 KB)

INTC1

CPU1 (PE1)

SEG

CPU

core

MPU

FPU

IPG

RH850 Datasheet(PDF) 32 Page - Renesas Technology Corp

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