RH850 datasheet(24/422 Pages) RENESAS

24 / 422 page

RH850/F1KH, RH850/F1KM

Section 1B Overview of RH850/F1KM-S4, RH850/F1KM-S2

R01DS0442EJ0100 Rev.1.00

Page 24 of 422

Sep 15, 2023

P-Bus

Peripheral

Group 1

Peripheral

Group 2

Peripheral

Group 3

Peripheral

Group 4

Peripheral

Group 5

System interconnect

Local RAM

(128 KB)

Debug

Global RAM

(96 KB)

/Retention RAM

(32 KB)

DMA

(32 ch)

System control

LVI

CLMA

(4 ch)

LVI

MainOSC

LS IntO SC

HS IntOSC

PLL1

STBC

CVM

POC

LPS

Code flash

(2 MB)

OSTM

(5 units)

CSIH

(4 ch)

CSIG

(1 ch)

RS-CANFD

(8 ch)

WDTA

(2 units)

TAUD

(1 unit)

TAUB

(1 unit)

TAUJ

(4 units)

RTCA

(1 unit)

ENCA

(1 unit)

Motor

control

PWM-Diag

(44 ch)

INTC2

DMA re g

ADCA0

RLIN3

(3 ch)

RLIN2

(3 ch)

RIIC

(2 ch)

(8 ch)

Flash

controller

DCRA

(4 ch)

Por t

RSENT

(1 ch)

Data flash

(128 KB)

ICUMD

PLL0

Flash interface

INTC1

CPU1 (PE1)

SEG

CPU

core

MPU

FPU

IPG

Figure 1B.6

Internal Block Diagram (RH850/F1KM-S2 100-Pin Version)

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