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RL78 Datasheet(PDF) 48 Page - Renesas Technology Corp |
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RL78 Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 146 page  RL78/F15 3. ELECTRICAL SPECIFICATIONS (GRADE L) R01DS0461EJ0110 Rev.1.10 Page 48 of 143 Jan 30, 2026 (TA = -40 to +105 °C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/3) Items Symbol Conditions MIN. TYP. MAX. Unit Supply current Notes 1, 3 IDD2 HALT mode Note 2 High-speed on-chip oscillator clock operation fIH = 64 MHz fCLK = 32 MHz Note 5 1.3 11.0 mA fIH = 32 MHz fCLK = fIHNote 5 1.0 10.0 mA fIH = 1 MHz fCLK = fIHNote 5 0.3 1.7 mA Resonator operation fMX = 20 MHz fCLK = fMXNote 6 0.7 7.0 mA fMX = 1 MHz fCLK = fMXNote 6 0.2 1.7 mA Resonator operation (PLL operation) (PLL input clock = fMX) fPLL = 64 MHz, fMX = 8 MHz fCLK = 32 MHz Note 7 1.2 11.0 mA fPLL = 32 MHz, fMX = 8 MHz fCLK = 32 MHz Note 7 1.1 10.0 mA fPLL = 32 MHz, fMX = 4 MHz fCLK = 32 MHz Note 7 1.0 10.0 mA Subsystem clock operation fSUB = 32.768 kHz fCLK = fSUBNote 8 0.7 90.0 μA Low-speed on-chip oscillator clock operation fIL = 15 kHz fCLK = fILNote 9 0.7 80.0 μA IDD3 STOP mode Note 4 TA = +25 °C 0.5 μA TA = +50 °C 4.5 TA = +70 °C 8.0 TA = +105 °C 50.0 Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, EVDD1, VSS, EVSS0, or EVSS1. However, not including the current flowing into the I/O buffer and on-chip pull-up/pull-down resistors. 2. When HALT mode is entered during fetch from the flash memory. 3. The values below the MAX. column include the peripheral operation current and STOP leakage current. However, the watchdog timer, LVD circuit, A/D converter, D/A converter, and comparator are stopped. 4. When high-speed system clock, subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low- speed on-chip oscillator clock are stopped. 5. When high-speed system clock, subsystem clock, PLL clock, and low-speed on-chip oscillator clock are stopped. 6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 8. When high-speed system clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. 9. When high-speed system clock, subsystem clock, PLL clock, and high-speed on-chip oscillator clock are stopped. |
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