RL78 datasheet(53/146 Pages) RENESAS

53 / 146 page

RL78/F15

3. ELECTRICAL SPECIFICATIONS (GRADE L)

R01DS0461EJ0110 Rev.1.10

Page 53 of 143

Jan 30, 2026

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Port output rise time, port

output fall time

tRO, tFO

P00 to P07, P10 to

P17, P20 to P27, P30

to P32, P35 to P37,

P40 to P47, P50 to

P57, P60 to P67, P70

to P77, P106, P107,

P110 to P117, P120,

P125 to P127, P130 to

P136, P140 to P147,

P150 to P157, P160 to

P167

(normal slew rate)

C = 30 pF

4.0 V

≤ EVDD0 ≤ 5.5 V

2.7 V

≤ EVDD0 < 4.0 V

P10, P12, P14, P30,

P120, P140

(special slew rate)

C = 30 pF

4.0 V

≤ EVDD0 ≤ 5.5 V

25 Note

2.7 V

≤ EVDD0 < 4.0 V

100

Note TA = +25

°C, EVDD0 = 5.0 V

Caution Excluding the error in oscillation frequency accuracy.

Remark fMCK: Timer array unit operation clock frequency

AC Timing Test Points

Test points

VIH

VIL

VIH

VIL

External System Clock Timing

EXCLK

0.8 VDD (MIN.)

0.2 VDD (MAX.)

1/fEX

tEXL

tEXH

EXCLKS

0.8 VDD (MIN.)

0.2 VDD (MAX.)

1/fEXS

tEXLS

tEXHS

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