RL78 datasheet(52/146 Pages) RENESAS

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RL78/F15

3. ELECTRICAL SPECIFICATIONS (GRADE L)

R01DS0461EJ0110 Rev.1.10

Page 52 of 143

Jan 30, 2026

3.4 AC Characteristics

3.4.1 Basic Operation

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Instruction cycle (minimum

instruction execution time)

TCY

High-speed on-chip oscillator clock operation

0.03125

μs

High-speed system clock operation

0.05

μs

PLL clock operation

0.03125

μs

Subsystem clock operation

28.5

30.5

34.5

μs

Low-speed on-chip oscillator clock operation

66.6

μs

In self programming mode

0.03125

μs

CPU/peripheral hardware

clock frequency

fCLK

0.03125

66.6

μs

External system clock

frequency

fEX

1.0

20.0

MHz

fEXS

kHz

External system clock

input high-level width, low-

level width

tEXH, tEXL

tEXHS,

tEXLS

13.7

μs

TI00 to TI07, TI10 to TI17,

TI20 to TI27 input high-

level width, low-level width

tTIH,

tTIL

1/fMCK+10

TO00 to TO07, TO10 to

TO17, TO20 to TO27

output frequency

fTO

All TO pins,

Normal slew rate,

C = 30 pF

4.0 V

≤ EVDD0 ≤ 5.5 V

MHz

2.7 V

≤ EVDD0 < 4.0 V

MHz

TO01, TO06, TO07,

TO11, TO13 only,

Special slew rate,

C = 30 pF

MHz

PCLBUZ0 output

frequency

fPCL

Normal slew rate

C = 30 pF

4.0 V

≤ EVDD0 ≤ 5.5 V

MHz

2.7 V

≤ EVDD0 < 4.0 V

MHz

Special slew rate

C = 30 pF

MHz

Timer RJ input cycle

TRJIO0

100

Timer RJ input high-level

width, low-level width

tWH,

tWL

TRJIO0

Interrupt input high-level

width, low-level width

tINTH,

tINTL

INTP0 to INTP15 Note

μs

KR0 to KR7 key interrupt

input low-level width

tKR

250

RESET low-level width

tRSL

μs

Note Pins RESET, INTP0 to INTP3, INTP12, and INTP13 have noise filters for transient levels lasting less than 100 ns.

Caution Excluding the error in oscillation frequency accuracy.

Remark fMCK: Timer array unit operation clock frequency

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