RL78 datasheet(21/146 Pages) RENESAS

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RL78/F15

2. PIN FUNCTIONS

R01DS0461EJ0110 Rev.1.10

Page 21 of 143

Jan 30, 2026

(2/3)

Function

Name

I/O

Function

After Reset

Alternate Function

P60

I/O

Port 6

Input of P62 and P63 can be set to TTL input buffer.

Use of an on-chip pull-up resistor can be specified by a software setting.

Output from P60 to P63 can be set to N-ch open-drain output.

For input to P60 to P63, the threshold level can be specified.

Input port

(SCK00)/(SCL00)/CRXD1/IERXD

P61

(SI00)/(SDA00)/(RXD0)/

CTXD1/IETXD

P62

(SO00)/(TXD0)/SCLA0

P63

(SSI00)/SDAA0

P64

(TI14)/(TO14)/(SNZOUT3)

P65

(TI16)/(TO16)/(SNZOUT2)

P66

(TI00)/(TO00)

P67

(TI02)/(TO02)

P70

I/O

Port 7

Input of P70, P71, and P73 can be set to TTL input buffer.

P70 to P74 can be set to analog input.

Use of an on-chip pull-up resistor can be specified by a software setting.

Output from P70 to P72 can be set to N-ch open-drain output.

For input to P70, P71, P73, and P75 to P77, the threshold level can be

specified.

Analog input

port

ANI26/KR0/TI15/TO15/INTP8/

SI11/SDA11/SNZOUT4

P71

ANI27/KR1/TI17/TO17/INTP6/

SCK11/SCL11/SNZOUT5

P72

ANI28/KR2/(CTXD0)/SO11/

SNZOUT6

P73

ANI29/KR3/(CRXD0)/SSI11/

SNZOUT7

P74

ANI30/KR4/(SO10)/(TXD1)

P75

Input port

KR5/(SI10)/(RXD1)

P76

KR6/(SCK10)

P77

KR7/(SSI10)/INTP12

P80

I/O

Port 8

P80 to P87 can be set to analog input.

Analog input

port

ANI2/ANO0

P81

ANI3/IVCMP00

P82

ANI4/IVCMP01

P83

ANI5/IVCMP02

P84

ANI6/IVCMP03

P85

ANI7/IVREF0

P86

ANI8

P87

ANI9

P90

I/O

Port 9

P90 to P97 can be set to analog input.

Analog input

port

ANI10

P91

ANI11

P92

ANI12

P93

ANI13

P94

ANI14

P95

ANI15

P96

ANI16

P97

ANI17

P100

I/O

Port 10

P100 to P105 can be set to analog input.

For P106 and P107, use of an on-chip pull-up resistor can be specified

by a software setting.

For input to P107, the threshold level can be specified.

Analog input

port

ANI18

P101

ANI19

P102

ANI20

P103

ANI21

P104

ANI22

P105

ANI23

P106

Input port

(LTXD1)

P107

(LRXD1)

P120

I/O

Port 12

Input of P125 can be set to TTL input buffer.

P120 and P125 can be set to analog input.

For P120 and P125 to P127, use of an on-chip pull-up resistor can be

specified by a software setting.

Output from P120 can be set to N-ch open-drain output.

For input to P125, the threshold level can be specified.

Analog input

port

ANI25/TI07/TO07/TRDIOD0/

SO01/INTP4

P121

Input

Input port

P122

X2/EXCLK

P123

XT1

P124

XT2/EXCLKS

P125

I/O

Analog input

port

ANI24/TI03/TO03/TRDIOB0/

SSI01/INTP1/SNZOUT1

P126

Input port

(TI01)/(TO01)

P127

(TI03)/(TO03)

Remark Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection

registers (PIOR).

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