ETA3001

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4

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ETA3001 Rev 1.2

TSD_HYST

TSD Hysteresis

30

C

PIN DESCRIPTION

PIN#

NAME

DESCRIPTION

1

BATP

Sense voltage input for top cell. Connect a 10µF capacitor between BATP

and BATC.

2

HGATE

Control high side external MOSFET.

3

SW

Switching node. Connected to an inductor.

4

LGATE

Control low side external MOSFET.

5

BATN

Negative terminal sense voltage input and common

Ground pin.

6

BIAS

Bias pin. Connect a 10nF capacitor from BIAS to SW.

7

ISET

Balancing current setting pin. Connect a resistor from SW to an inductor to

program

the

balancing

current.

Under

an

extremely

high

noise

environment, a 1nF capacitor between ISET pin and SW pin can improve

the ISET voltage stability, so a capacitor position reservation here is

recommended.

8

BATC

Sense voltage input for bottom cell. Connect a 10µF capacitor between

BATC and BATN.

Exposed Pad

EP

Connect it to GND.

FUNCTIONAL BLOCK DIAGRAM

ETA3001

Bandgap

& VDD

& BIAS

& OVP

& TSD

1uA

UVLO

Timer

Control

Balance

Current

Sense

Battery

Sense

VDD

ISET

BATP

Balance

Control

BATC

BIAS

Upper Cell

Driver

Lower Cell

Driver

SW

HGATE

LGATE

BATN

Figure 2: Functional Block Diagram