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3.17.1

IFR and IER Registers

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

Table 3-77. Interrupt Table (continued)

SOFTWARE

LOCATION

NAME

(TRAP)

PRIORITY

FUNCTION

(HEX BYTES)

EQUIVALENT

DMAC0

SINT18

DMA Channel #0 interrupt

–

SINT19

Software interrupt #19

DMAC2

SINT20

DMA Channel #2 interrupt

DMAC3

SINT21

DMA Channel #3 interrupt

TINT1

SINT22

Timer #1 interrupt

IIC

SINT23

I2C interrupt

BERR

SINT24

Bus Error interrupt

DLOG

SINT25

Data Log interrupt

RTOS

SINT26

Real-time Operating System interrupt

–

SINT27

Software interrupt #27

–

SINT28

Software interrupt #28

–

SINT29

Software interrupt #29

–

SINT30

Software interrupt #30

SINT31

Software interrupt #31

The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during

normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that

are currently pending.

The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the

real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing

(IER0/1) is used and DBIER0/1 are ignored.

A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted

in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled

in an interrupt enable register (IER0 or IER1).

Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its

corresponding bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using

the real-time emulation mode.

A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears

IFR0/1 to 0 but does not affect IER0/1 and DBIER0/1.

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