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3.18 Notice Concerning TCK

-1

nanoseconds (ns)

2.5 V

0.6 V

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

Under certain conditions, the emulation hardware may corrupt the emulation control state machine or may

cause it to lose synchronization with the emulator software. When emulation commands fail as a result of

the problem, Code Composer Studio™ Integrated Development Environment (IDE) may be unable to start

or it may report errors when interacting with the TMS320C55x™ DSP (for example, when halting the CPU,

reaching a breakpoint, etc.).

This phenomenon is observed when an erroneous clock edge is generated from the TCK signal inside the

C55x™ DSP. This can be caused by several factors, acting independently or cumulatively:

• TCK transition times (as measured between 2.4 V and 0.8 V) in excess of 3 ns.

• Operating the C55x DSP in a socket, which can aggravate noise or glitches on the TCK input.

• Poor signal integrity on the TCK line from reflections or other layout issues.

A TCK edge that can cause this problem might look similar to the one shown in Figure 3-53. A TCK edge

that does not cause the problem looks similar to the one shown in Figure 3-54. The key difference

between the two figures is that Figure 3-54 has a clean and sharp transition whereas Figure 3-53 has a

"knee" in the transition zone. Problematic TCK signals may not have a knee that is as pronounced as the

one in Figure 3-53. Due to the TCK signal amplification inside the chip, any perturbation of the signal can

create erroneous clock edges.

As a result of the faster edge transition, there is increased ringing in Figure 3-54. As long as the ringing

does not cross logic input thresholds (0.8 V for falling edges, and 2.4 V for rising edges), this ringing is

acceptable.

When examining a TCK signal for this issue, either in board simulation or on an actual board, it is very

important to probe the TCK line as close to the DSP input pin as possible. In simulation, it should not be

difficult to probe right at the DSP input. For most physical boards, this means using the via for the TCK

pad on the back side of the board. Similarly, ground for the probe should come from one of the nearby

ground pad vias to minimize EMI noise picked up by the probe.

Figure 3-53. Bad TCK Transition

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