LAN9312 datasheet(162/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

162

SMSC LAN9312

DATASHEET

Chapter 13 GPIO/LED Controller

13.1

Functional Overview

The GPIO/LED Controller provides 12 configurable general purpose input/output pins, GPIO[11:0].

These pins can be individually configured to function as inputs, push-pull outputs, or open drain outputs

and each is capable of interrupt generation with configurable polarity. Two of the GPIO pins (GPIO[9:8])

can be used for IEEE 1588 timestamp functions, allowing GPIO driven 1588 time clock capture when

configured as an input, or GPIO output generation based on an IEEE 1588 clock target compare event.

In addition, 8 of the GPIO pins can be alternatively configured as LED outputs. These pins, GPIO[7:0]

(nP1LED[3:0] and nP2LED[3:0]), may be enabled to drive Ethernet status LEDs for external indication

of various attributes of the switch ports.

GPIO and LED functionality is configured via the GPIO/LED System Control and Status Registers

(CSRs), accessible through the Host Bus Interface (HBI). These registers are defined in Section

14.2.3, "GPIO/LED," on page 192.

13.2

GPIO Operation

The GPIO controller is comprised of 12 programmable input/output pins. These pins are individually

configurable via the GPIO CSRs. On application of a chip-level reset:

All GPIOs are set as inputs (GPDIR[11:0] cleared in General Purpose I/O Data & Direction Register

(GPIO_DATA_DIR))

All GPIO interrupts are disabled (GPIO[11:0]_INT_EN cleared in General Purpose I/O Interrupt

Status and Enable Register (GPIO_INT_STS_EN)

All GPIO interrupts are configured to low logic level triggering (GPIO_INT_POL[11:0] cleared in

General Purpose I/O Configuration Register (GPIO_CFG))

Note:

GPIO[7:0] may be configured as LED outputs by default, dependant on the LED_en_stap[7:0]

configuration straps. Refer to Section 13.3, "LED Operation" for additional information.

The direction and buffer type of all 12 GPIOs are configured via the General Purpose I/O Configuration

direction of each GPIO, input or output, should be configured first via its respective GPIO direction bit

(GPDIR[11:0]) in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). When

configured as an output, the output buffer type for each GPIO is selected by the GPIOBUF[11:0] bits

in the General Purpose I/O Configuration Register (GPIO_CFG). Push/pull and open-drain output

buffers are supported for each GPIO. When functioning as an open-drain driver, the GPIO output pin

is driven low when the corresponding data register bit (GPIOD in the General Purpose I/O Data &

Direction Register (GPIO_DATA_DIR)) is cleared to 0, and is not driven when set to 1.

When a GPIO is enabled as an output, the value output to the GPIO pin is set via the corresponding

GPIOD[11:0] bit in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). For GPIOs

configured as inputs, the corresponding GPIOD[11:0] bit reflects the current state of the GPIO input.

Note:

For GPIO[9:8], the pin direction is a function of both the GPDIR[9:8] bits of the General

Purpose I/O Data & Direction Register (GPIO_DATA_DIR) and the 1588_GPIO_OE[9:8] bits in

the General Purpose I/O Configuration Register (GPIO_CFG).

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