LAN9312 datasheet(452/458 Pages) SMSC

Part #	LAN9312

Description	High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

PDF	458 Pages

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Manufacturer	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

452

SMSC LAN9312

DATASHEET

15.5.9

TX Data FIFO Direct PIO Write Cycle Timing

Please refer to Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111 for a functional

description of this mode.

Note:

A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The

cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-

asserted in any order.

Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing

Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcycle

Write Cycle Time

tcsl

nCS, nWER Assertion Time

tcsh

nCS, nWR De-assertion Time

tasu

Address, FIFO_SEL Setup to nCS, nWR Assertion

tah

Address, FIFO_SEL Hold Time

tdsu

Data Setup to nCS, nWR De-assertion

tdh

Data Hold Time

tah

tdsu

A[2], END_SEL

nCS, nWR

D[31:0]

FIFO_SEL

tdh

tcsh

tcycle

tcsl

tasu

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