LAN9312 datasheet(449/458 Pages) SMSC

Part #	LAN9312

Description	High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

PDF	458 Pages

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Manufacturer	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

449

Revision 1.2 (04-08-08)

DATASHEET

15.5.6

RX Data FIFO Direct PIO Read Cycle Timing

Please refer to Section 8.4.6, "RX Data FIFO Direct PIO Reads," on page 108 for a functional

description of this mode.

Note:

A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle

ends when either or both nCS and nRD are de-asserted. They may be asserted and de-

asserted in any order.

Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing

Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcycle

Read Cycle Time

tcsl

CS, nRD Assertion Time

tcsh

nCS, nRD De-assertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

tah

A[x:2], END_SEL

nCS, nRD

D[31:0]

FIFO_SEL

tasu

tcycle

tcsl

tcsh

tdoff

tcsdv

tdon

tdoh

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