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LAN9312 Datasheet(PDF) 447 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 447 Page - SMSC Corporation |
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447 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 447 Revision 1.2 (04-08-08) DATASHEET 15.5.4 PIO Read Cycle Timing Please refer to Section 8.4.4, "PIO Reads," on page 106 for a functional description of this mode. Note: A host PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. These signals may be asserted and de-asserted in any order. Figure 15.4 PIO Read Cycle Timing Table 15.8 PIO Read Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Read Cycle Time 45 nS tcsl nCS, nRD Assertion Time 32 nS tcsh nCS, nRD De-assertion Time 13 nS tcsdv nCS, nRD Valid to Data Valid 30 nS tasu Address setup to nCS, nRD Valid 0 nS tah Address Hold Time 0 nS tdon Data Buffer Turn On Time 0 nS tdoff Data Buffer Turn Off Time 9 nS tdoh Data Output Hold Time 0 nS tah A[x:2], END_SEL nCS, nRD D[31:0] tasu tcycle tcsh tcsl tcsdv tdon tdoh tdoff |
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