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LAN9312 Datasheet(PDF) 451 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 451 Page - SMSC Corporation |
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451 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 451 Revision 1.2 (04-08-08) DATASHEET 15.5.8 PIO Write Cycle Timing Please refer to Section 8.4.8, "PIO Writes," on page 110 for a functional description of this mode. Note: A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. These signals may be asserted and de-asserted in any order. Figure 15.8 PIO Write Cycle Timing Table 15.12 PIO Write Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Write Cycle Time 45 nS tcsl nCS, nWR Assertion Time 32 nS tcsh nCS, nWR De-assertion Time 13 nS tasu Address Setup to nCS, nWR Assertion 0 nS tah Address Hold Time 0 nS tdsu Data Setup to nCS, nWR De-assertion 7 nS tdh Data Hold Time 0 nS tah A[x:2], END_SEL nCS, nWR D[31:0] tasu tcsl tcycle tcsh tdh tdsu |
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