LAN9312 datasheet(450/458 Pages) SMSC

450 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

450

SMSC LAN9312

DATASHEET

15.5.7

RX Data FIFO Direct PIO Burst Read Cycle Timing

Please refer to Section 8.4.7, "RX Data FIFO Direct PIO Burst Reads," on page 109 for a functional

description of this mode.

Note:

A RX Data FIFO direct PIO burst read cycle begins when both nCS and nRD are asserted.

The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and

de-asserted in any order.

Note:

Fresh data is supplied each time A[2] toggles.

Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing

Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcsh

nCS, nRD De-assertion Time

tcsdv

nCS, nRD Valid to Data Valid

tacyc

Address Cycle Time

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tadv

Address Stable to Data Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

A[2]

nCS, nRD

D[31:0]

END_SEL

FIFO_SEL

tasu

tacyc

tadv

tcsdv

tdon

tacyc

tcsh

tadv

tah

tdoh

tdoff

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