LAN9312 datasheet(448/458 Pages) SMSC

Part #	LAN9312

Description	High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

PDF	458 Pages

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Manufacturer	SMSC [SMSC Corporation]

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

448

SMSC LAN9312

DATASHEET

15.5.5

PIO Burst Read Cycle Timing

Please refer to Section 8.4.5, "PIO Burst Reads," on page 107 for a functional description of this mode.

Note:

A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends

when either or both nCS and nRD are de-asserted. These signals may be asserted and de-

asserted in any order.

Note:

Fresh data is supplied each time A[2] toggles.

Figure 15.5 PIO Burst Read Cycle Timing

Table 15.9 PIO Burst Read Cycle Timing Values

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcsh

nCS, nRD De-assertion Time

tcsdv

nCS, nRD Valid to Data Valid

tacyc

Address Cycle Time

tasu

Address Setup to nCS, nRD Valid

tadv

Address Stable to Data Valid

tah

Address Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

A[4:2]

nCS, nRD

D[31:0]

A[x:5], END_SEL

tasu

tacyc

tah

tcsh

tadv

tcsdv

tdon

tdoh

tdoff

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