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LAN9312 Datasheet(PDF) 445 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 445 Page - SMSC Corporation |
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445 / 458 page ![]() High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 445 Revision 1.2 (04-08-08) DATASHEET 15.5.2 Reset and Configuration Strap Timing This diagram illustrates the nRST pin timing requirements and its relation to the configuration strap pins and output drive. Assertion of nRST is not a requirement. However, if used, it must be asserted for the minimum period specified. Please refer to Section 4.2, "Resets," on page 36 for additional information. Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 4.2.4, "Configuration Straps," on page 40 for details. Figure 15.2 nRST Reset Pin Timing Table 15.6 nRST Reset Pin Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS trstia nRST input assertion time 200 μS tcss Configuration strap pins setup to nRST deassertion 200 nS tcsh Configuration strap pins hold after nRST deassertion 10 nS todad Output drive after deassertion 30 nS tcss nRST Configuration Strap Pins trstia tcsh Output Drive todad |
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