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M58BF008

Table 8. Status Register Bits

Mne-

monic

Bit

Name

Logic

Level

Definiti on

Note

P/ECS

P/E.C. Status

’1’

Ready

Indicates the P/E.C. status, check during

Program or Erase

’0’

Busy

PESS

Program/Erase

Suspend Status

‘1’

Suspend

On Program/Erase Suspend instruction both

P/ECS and PESS bits are set to ‘1’.

Either ES bit or PS bit is set to ‘1’.

PESS and either ES or PS bits remain at ‘1’

until Erase Resume instruction is given.

‘0’

In Progress or

Completed

Erase Status

’1’

Erase Error or

Erase Suspend

ES bit is set to ‘1’ if either PESS instruction is

given or Erase operation fails. If ES bit is ‘1’,

check PESS bit.

’0’

Erase Success

Program Status

’1’

Program Error or

Program Suspend

PS bit is set to ‘1’ if either PESS instruction is

given or Program operation fails. If PS bit is ‘1’,

check PESS bit.

’0’

Program Success

VPPS

VPP Status

’1’

VPP Invalid

VPPS bit is set to ‘1’ if initially VPP is not VPPH

nor VPP1, when Program or Erase Instruction

are executed.

’0’

VPP OK

Reserved

OBEB

Overlay Block

Enable Bit

’1’

Enabled

OBEB bit is set to ‘1’ when Overlay Block is

Enabled.

’0’

Disabled

OBS

Overlay Block

Status

’1’

Activated

OBS bit is set to ‘1’ when OBEB is ‘1’ and VPP

is in the range VPP1 or VPPH.

’0’

Not Activated

Erase (EE). The Erase instruction consists of two

write cycles, the first is the erase set-up command

20h at the address 00000h. This is followed by the

Erase Confirm command D0h written to an ad-

dress within the block to be erased. If the second

is not the Erase Confirm command the Status

tion aborts. While erasing is in progress only the

Read Status Register and Erase Suspend instruc-

tions are valid.

Blocks are erased one at a time. An erase opera-

tion sets all bits in a block to ’1’. The erase algo-

rithm automatically programs all bits to ’0’ before

erasing the block to all ’1’s.

Read operations output the Status Register after

the erase operation has started. The Status Reg-

ister bit 7 is ’0’ while the erase is in progress and is

set to ’1’ when it is completed. After completion the

Status Register bit 5 is set to ’1’ if there has been

an erase failure.

Erasure should not be attempted when the VPP

Program/Erase Supply Voltage is out of the range

VPP1 or VPPH as the results will be uncertain. The

Status Register bit 3 is set to ’1’ if VPP is not within

the allowed ranges when erasing is attempted or if

it falls out of the ranges during erase execution.

The erase operation aborts if VPP drops out of the

allowed range or if Reset/Power-down RP falls to

VIL. As data integrity cannot be guaranteed when

the erase operation is aborted, the erase must be

repeated.

A Clear Status Register instruction must be given

to clear the Status Register bits.

Overlay Block Erase (OBEE). The

Overlay

Block Erase instruction consists of two write cy-

cles, the first is the Overlay block erase set-up

command 02h at the address 00000h. This is fol-

lowed by the Overlay Block Erase Confirm com-

mand 0Dh written to an address within the Overlay

block. If the second is not the Overlay Block Erase

Confirm command the Status Register bit 5 is set

to ’1’ and the instruction aborts. While erasing is in

progress only the Read Status Register instruction

is valid.

The operation is executed as described for the

Erase (EE) instruction of the Main memory array.

A Clear Status Register instruction must be given

to clear the Status Register bits.

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