M58BF008 datasheet(12/36 Pages) STMICROELECTRONICS

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M58BF008

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Program (PG). The Program instruction consists

of two write cycles, the first is the program set-up

command 40h at the address 00000h. This is fol-

lowed by a second write cycle to latch the address

and data to be programmed. This second com-

mand starts the P/E.C. A program operation can

be aborted by writing FFFFFFFFh to any address

after the program set-up command has been giv-

en. While programming is in progress only the

Read Status Register and Program Suspend in-

structions are valid.

Read operations output the Status Register after

the program operation has started. The Status

progress and is set to ’1’ when it is completed. Af-

ter completion the Status Register bit 4 is set to ’1’

if there has been a programming failure.

Programming should not be attempted when the

VPP Program/Erase Supply Voltage is out of the

range VPP1 or VPPH as the results will be uncer-

tain. The Status Register bit 3 is set to ’1’ if VPP is

not within the allowed ranges when programming

is attempted or if it falls out of the ranges during

program execution.

The program operation aborts if VPP drops out of

the allowed ranges or if Reset/Power-Down RP

falls to VIL. As data integrity cannot be guaranteed

when the program operation is aborted, the mem-

ory block must be erased and programming re-

peated.

A Clear Status Register instruction must be given

to clear the Status Register bits.

Overlay Block Program (OBPG). The

Overlay

Block Program instruction consists of two write cy-

cles, the first is the program set-up command 04h

at the address 00000h. This is followed by a sec-

ond write cycle to latch the address and data to be

programmed. This second command starts the P/

E.C.

The operation is executed as described for the

Program (PG) instruction of the Main memory ar-

ray.

While programming of the Overlay block in

progress only the Read Status Register instruction

is valid.

Program/Erase Suspend (PES). As

memory

erasure takes of the order of seconds to complete

and programming a few microseconds, a Pro-

gram/Erase Suspend instruction is implemented.

Program/Erase Suspend interrupts the operations

to allow reading or programming in a block other

than one in which program or erase is suspended.

A Program/Erase Suspend instruction is accepted

only during a Program or Erase instruction. When

the Program/Erase Suspend command is written

to the Command Interface, the P/E.C. freezes the

program or erase operation. The suspended pro-

gram or erase operation may be restarted by using

the Program/Erase Resume instruction. Program/

Erase Suspend is not allowed during the Overlay

block program/erase operation and the command

is ignored.

The Program/Erase Suspend instruction consists

of one write cycle giving the command B0h at the

address 00000h.

If a program operation is in progress when the in-

struction is given, the Status Register bits 4 and 6

are set to ’1’ after it has been suspended. If an

erase operation is in progress when the instruction

is given, the Status Register bits 5 and 6 are set to

’1’ after it has been suspended.

The valid instructions that may be given to the

memory while programing is suspended are

– Read Memory Array (RD)

– Read Status Register (RSR)

– Read Electronic Signature (RSIG)

– Program/Erase Resume (PER)

In addition, while erasure is suspended, the Pro-

gram (PG) instruction may be given.

In Program/Erase Suspend mode the memory can

be placed in a pseudo-standby mode by taking

Chip Enable /E to VIH to reduce power consump-

tion.

Program/Erase Resume (PER). If a Program/

Erase Suspend instruction has previously been

executed, then the operation may be resumed by

giving the command D0h at the address 00000h.

The Status Register bits 4, 5 and 6 are cleared

when program or erase resumes. A Read Memory

Array instruction will output the Status Register af-

ter program or erase is resumed.

Suggested flow charts for software that uses pro-

gramming, erasure and program/erase suspend/

resume operations are shown in Figures 11, 12,

13 and 14.

Asynchronous/Synchronous Read Toggle (ART).

Asynchronous Read Memory Array is the memory

default at power-up or when returning from Power-

Down. To read data in Synchronous mode, either

single or burst, the Asynchronous/Synchronous

Read Toggle instruction must be used.

The Asynchronous/Synchronous Read Toggle in-

struction consists of one write cycle giving the

command 60h at the address 00000h. Two con-

secutive instructions are not recognised and an-

other Instruction, for example the Read Memory

Array, must be given before another Asynchro-

nous/Synchronous Read Toggle will be recogn-

ised.

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