M58BF008 datasheet(14/36 Pages) STMICROELECTRONICS

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M58BF008

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CONFIGURATION

The M58BF008 is configured during testing which

sets the default for the write and burst interface.

The settings are:

Write Interface. The write interface can be set

permanently to either Asynchronous or Synchro-

nous. Note that the read interface is not affected

by this configuration and defaults to Asynchronous

read at power-up, it can be toggled to Synchro-

nous read and back using the Asynchronous/Syn-

chronous Read Toggle Instruction.

Wrap/No-Wrap. The burst function can be set to

default to wrap or no-wrap. The behaviour is

shown in Table 13. Wrap/No-wrap can be toggled

using the Wrap/No-wrap Burst Toggle Instruction.

Critical Word and Burst Word Latency Times.

The Critical Word and Burst Word latency times

can be set permanently to

– Critical Word Latency Time X = 3 or 4

– Burst Word Latency Time Y = 1 or 2

A burst sequence is described as X-Y-Y-Y.

Table 11. Configuration

Table 12. Wrap/No-wrap Burst Sequence

Name

Option 1

Optio n 2

Write Interface

Synchronous

Asynchronous

Wrap/No-wrap Burst

Wrap

No-wrap

Critical Word Latency Time (X)

Burst Word Latency Time (Y)

First Burst Address A1-A0

Data Wrap

Data No-wrap

Double-Word 0

⇒ 1 ⇒ 2 ⇒ 3

Double-Word 0

⇒ 1 ⇒ 2 ⇒ 3

Double-Word 1

⇒ 2 ⇒ 3 ⇒ 0

Double-Word 1

⇒ 2 ⇒ 3

Double-Word 2

⇒ 3 ⇒ 0 ⇒ 1

Double-Word 2

⇒ 3

Double-Word 3

⇒ 0 ⇒ 1 ⇒ 2

Double-Word 3

POWER SUPPLY

The M58BF008 places itself in one of three differ-

ent modes depending on the status of the control

signals which define decreasing levels of current

consumption. This minimises the memory power

consumption, allowing an overall decrease in the

system power consumption without affecting per-

formance. A different recovery time is, however,

linked to the different modes - see the AC timing

tables.

Active Power mode. When Chip Enable E is at

VIL and Reset/Power-Down RP is at VIH the mem-

ory is in Active Power mode. The DC characteris-

tics tables show the current consumption figures.

Standby mode. Refer to the Device Operating

section

Power-Down mode. Refer to the Device Operat-

ing section.

Power Up. The VDD Supply Voltage, VDDQ Input/

Output Supply Voltage and the VPP Program/

Erase Supply Voltage can be applied in any order.

The memory Command Interface is reset on pow-

er-up to Read Memory Array, but a negative tran-

sition on Chip Enable E or a change of the

addresses is required to ensure valid data is out-

put.

Care must be taken to avoid writes to the memory

when the VDD Supply Voltage is above VLKO and

VPP Program/Erase Supply Voltage powers-up

first. Writes can be inhibited by driving either Write

Enable W or Write/Read WR to VIH.

The memory is disabled until Reset/Power-Down

RP is up to VIH.

SUPPLY RAILS

Normal precautions must be taken for supply rail

decoupling. Each device in a system should have

the VDD,VDDQ and VPP rails decoupled with a

0.1

µF capacitor close to the package pins. PCB

track widths should be sufficient to carry the re-

quired program and erase currents on the VPP

supply.

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