S124 datasheet(3/107 Pages) RENESAS

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R01DS0264EU0140 Rev.1.40

Page 3 of 107

Sep 3, 2024

S124 Datasheet

1. Overview

Clock

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 Independent watchdog timer on-chip oscillator

 Clock out support.

See section 8, Clock Generation Circuit in Userʼs Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) is used to check the system clock

frequency with a reference clock signal by counting the number of pulses of the system clock

to be measured. The reference clock can be provided externally through a CACREF pin or

internally from various on-chip oscillators.

Event signals can be generated when the clock does not match or measurement ends.

This feature is particularly useful in implementing a fail-safe mechanism for home and

industrial automation applications.

See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in Userʼs Manual.

Interrupt Controller Unit (ICU)

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module and DMAC module. The ICU also controls NMI interrupts. See section 12, Interrupt

Controller Unit (ICU) in Userʼs Manual.

Key interrupt function (KINT)

A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting

a rising or falling edge to the key interrupt input pins. See section 17, Key Interrupt Function

(KINT) in Userʼs Manual.

Low Power Mode

Power consumption can be reduced in multiple ways, including setting clock dividers, stopping

modules, selecting power control mode in normal operation, and transitioning to low power

modes. See section 10, Low Power Modes in Userʼs Manual.

The Register Write Protection function protects important registers from being overwritten due

to software errors. See section 11, Register Write Protection in Userʼs Manual.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The

refresh-permitted period can be set to refresh the counter and used as the condition to detect

when the system runs out of control. See section 22, Watchdog Timer (WDT) in Userʼs

Manual.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the

timer operates with an independent, dedicated clock source, it is particularly useful in returning

the MCU to a known state as a fail safe mechanism when the system runs out of control. The

watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a

refresh of the count value in the registers. See section 23, Independent Watchdog Timer

(IWDT) in Userʼs Manual.

Table 1.4

Event Link

Feature

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 15, Event Link Controller (ELC) in

Userʼs Manual.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when

activated by an interrupt request. See section 14, Data Transfer Controller (DTC) in Userʼs

Manual.

Table 1.3

System (2 of 2)

Feature

Functional description

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