S124 datasheet(86/107 Pages) RENESAS

86 / 107 page

R01DS0264EU0140 Rev.1.40

Page 86 of 107

Sep 3, 2024

S124 Datasheet

2. Electrical Characteristics

2.9

POR and LVD Characteristics

Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this

voltage detection level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or

LVD2 is used for voltage detection.

Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.

Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.

Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.

Table 2.53

Power-on reset circuit and voltage detection circuit characteristics (1)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Voltage detection

level*1

Power-on reset (POR)

VPOR

1.27

1.42

1.57

Figure 2.66,

Figure 2.67

Voltage detection circuit (LVD0)*2

Vdet0_0

3.68

3.85

4.00

Figure 2.68

At falling edge

VCC

Vdet0_1

2.68

2.85

2.96

Vdet0_2

2.38

2.53

2.64

Vdet0_3

1.78

1.90

2.02

Vdet0_4

1.60

1.69

1.82

Voltage detection circuit (LVD1)*3

Vdet1_0

4.13

4.29

4.45

Figure 2.69

At falling edge

VCC

Vdet1_1

3.98

4.16

4.30

Vdet1_2

3.86

4.03

4.18

Vdet1_3

3.68

3.86

4.00

Vdet1_4

2.98

3.10

3.22

Vdet1_5

2.89

3.00

3.11

Vdet1_6

2.79

2.90

3.01

Vdet1_7

2.68

2.79

2.90

Vdet1_8

2.58

2.68

2.78

Vdet1_9

2.48

2.58

2.68

Vdet1_A

2.38

2.48

2.58

Vdet1_B

2.10

2.20

2.30

Vdet1_C

1.84

1.96

2.05

Vdet1_D

1.74

1.86

1.95

Vdet1_E

1.63

1.75

1.84

Vdet1_F

1.60

1.65

1.73

Voltage detection circuit (LVD2)*4

Vdet2_0

4.11

4.31

4.48

Figure 2.70

At falling edge

VCC

Vdet2_1

3.97

4.17

4.34

Vdet2_2

3.83

4.03

4.20

Vdet2_3

3.64

3.84

4.01

Table 2.54

Power-on reset circuit and voltage detection circuit characteristics (2) (1 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Wait time after power-on

Reset cancellation

LVD0:enable

tPOR

-1.7

LVD0:disable

tPOR

-1.3

Wait time after voltage

monitor 0,1,2 reset

cancellation

LVD0:enable*1

tLVD0,1,2

-0.6

LVD0:disable*2

tLVD1,2

-0.2

Response delay*3

tdet

350

μs

Figure 2.66, Figure 2.67

Minimum VCC down time

tVOFF

450

μs

Figure 2.66,

VCC = 1.0 V or above

S124 Datasheet(PDF) 86 Page - Renesas Technology Corp

S124 Datasheet(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL