S124 datasheet(49/107 Pages) RENESAS

49 / 107 page

R01DS0264EU0140 Rev.1.40

Page 49 of 107

Sep 3, 2024

S124 Datasheet

2. Electrical Characteristics

2.3.3

Reset Timing

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

Figure 2.29

Reset input timing at power-on

Figure 2.30

Reset input timing (1)

Table 2.23

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

Figure 2.29

Not at power-on

tRESW

μs

Figure 2.30

Wait time after RES cancellation

(at power-on)

LVD0 enabled*1

tRESWT

-0.7

Figure 2.29

LVD0 disabled*2

-0.3

Wait time after RES cancellation

(during powered-on state)

LVD0 enabled*1

tRESWT2

-0.5

Figure 2.30

LVD0 disabled*2

-0.05

Internal reset cancellation time (Watchdog

timer reset, SRAM parity error reset,

Software reset)

LVD0 enabled*1

tRESWT3

-0.6

LVD0 disabled*2

-0.15

VCC

RES

tRESWP

Internal reset

tRESWT

RES

Internal reset

tRESWT2

tRESW

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