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S124 Datasheet(PDF) 46 Page - Renesas Technology Corp

Part # S124
Description  S124 Microcontroller Group
PDF  107 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

S124 Datasheet(HTML) 46 Page - Renesas Technology Corp

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R01DS0264EU0140 Rev.1.40
Page 46 of 107
Sep 3, 2024
S124 Datasheet
2. Electrical Characteristics
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Note 4. See section 8, Clock Generation Circuit in Userʼs Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.22, Clock timing.
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in Userʼs Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.22, Clock timing.
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The 14-bit A/D converter cannot be used.
Note 3. See section 8, Clock Generation Circuit in Userʼs Manual for the relationship between ICLK, PCLKB, and PCLKD
frequencies.
Table 2.19
Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
*5
Unit
Operation
frequency
System clock (ICLK)*1, *2, *4
1.8 to 5.5 V
f
0.032768
-
1
MHz
Peripheral module clock (PCLKB)*4
1.8 to 5.5 V
-
-
1
Peripheral module clock (PCLKD)*3, *4
1.8 to 5.5 V
-
-
1
Table 2.20
Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
*5
Unit
Operation
frequency
System clock (ICLK)*1, *2, *4
1.6 to 5.5 V
f
0.032768
-
4
MHz
Peripheral module clock (PCLKB)*4
1.6 to 5.5 V
-
-
4
Peripheral module clock (PCLKD)*3, *4
1.6 to 5.5 V
-
-
4
Table 2.21
Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Operation
frequency
System clock (ICLK)*1, *3
1.8 to 5.5 V
f
27.8528
32.768
37.6832
kHz
Peripheral module clock (PCLKB)*3
1.8 to 5.5 V
-
-
37.6832
Peripheral module clock (PCLKD)*2, *3
1.8 to 5.5 V
-
-
37.6832



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