MK68564 datasheet(15/46 Pages) STMICROELECTRONICS

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in the Transmitter Control Register may also be u-

sed to signal the end of transmission. If this bit is set

to a one, its associated output pin (RTS) will go Low.

When this bit is reset to a zero, the RTS pin will go

High one bit time after the transmit clock that clocks

out the last stop bit, only if the transmit buffer is emp-

ty.

The Transmit Data output (TxD) is held marking

(High) after a reset or when the transmitter has no

data to send. Under program control, the Send

Break command can be issued to hold TxD spacing

(Low) until the command is cleared, even if the

transmitter is not enabled.

ASYNCHRONOUS RECEIVE

Asynchronous operation begins when the Receiver

Enable bit in the Receiver Control Register is set to

a one. If the Rx Auto Enables bit is also set, the Data

Carrier Detect (DCD) input pin must be Low as well.

The receiver will start assembling a character as

soon as a valid start bit is detected, if a clock mode

other than x1 is selected. A valid start bit is a High-

to-Low transition on the Receive Data input (RxD)

with the Low time lasting at least one-half bit time.

The High-to-Low transition starts an internal counter

and, at mid-bit time, the counter output is used to

sample the input signal to detect if it is still Low.

When this condition is satisfied, the following data

bits are sampled at mid-bit time until the entire char-

acter is assembled. The start bit detection logic is

then rearmed to detect the next High-to-Low trans-

ition. If the x1 clock mode is selected, the start bit de-

tection logic is disabled, and bit synchronization

must be accomplished externally. Receive data is

sampled on the rising edge of the Receiver Clock

(RxC).

The receiver may be programmed to assemble five

to eight data bits, plus a parity bit, into a character.

The character is right-justified in the shift register

and then transferred to the receive data FIFO. All da-

ta transfers to the FIFO are in eight-bit groups. If the

character length assembled is less than eight bits,

the receiver inserts ones in the unused bits. If parity

is enabled, the parity bit is transferred with the char-

acter, unless eight bits per character is program-

med, in which case, the parity bit is stripped from the

character before transfer.

A Receiver Interrupt request is generated every time

a character is shifted to the top of the receive data

FIFO, if Interrupt On All Receive Characters mode

is selected. The Rx Character Available bit in Status

is shifted to the top of the receive data FIFO. The Rx

Character Available bit is reset to a zero when the

receive buffer is read.

After a character is received, it is checked for the fol-

lowing error conditions :

Parity Error. If parity is enabled, the Parity Error bit

in Status Register 1 is set to a one whenever the pa-

rity bit of the received character does not match the

programmed parity. Once this bit is set, it remains

set (latched), until an Error Reset command

(Command 6) is issued. A Special Receive Condi-

tion interrupt is generated when this bit is set, if parity

is programmed as a Special Receive Condition.

Framing Error. The CRC/Framing Error bit in Sta-

tus Register 1 is set to a one, if the character is as-

sembled without a stop bit (a Low level detected ins-

tead of a stop bit). Thisbit is set only for the character

on which the framing error occurred ; it is updated

at every character time. Detection of a framing error

adds an additional one-half of a bit time to the char-

acter time, so the framing error is not interpreted as

a new start bit. A Special Receive Condition interrupt

is generated when this bit is set..

Overrun Error. If four or more characters are recei-

ved before the CPU (or other bus master) reads the

receive buffer, the fourth character assembled will

replace the third character in the receive data FIFO.

If more than four characters have been received, the

last character assembled will replace the third char-

acter in the data FIFO. The character that has been

written over is flagged with an overrun error in the

error FIFO.

When this character is shifted to the top of the re-

ceive data FIFO, the Receive Overrun Error bit in

Status Register 1 is set to a one ; the error bit is lat-

ched in the status register, and a Special Receive

Condition interrupt is generated. Like Parity Error,

this bit can only be reset by an Error Reset

Command.

Break Condition. A break character is defined as

a start bit, an all zero data word, and a zero in place

of the stop bit. When a break character is detected

in the receive data stream, the Break/Abort bit in

Status Register 0 is set to a one, and an Exter-

nal/Status interrupt is requested. This interrupt is

then followed by a Framing Error interrupt request

when the CRC/Framing Error bit in Status Register

1 is set. A Reset External/Status Interrupts

command (Command 2) should be issued to reini-

tialize the break detection interrupt logic. The recei-

ver will monitor the data stream input for the termi-

nation of the break sequence. When this condition

is detected, the Break/Abort bit will be reset, if

MK68564

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