MK68564 datasheet(35/46 Pages) STMICROELECTRONICS

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ta Register is not affected by a channel or hardware

reset.

TIME CONSTANT REGISTER (TCREG)

This register contains the time constant used by the

down counter in the baud rate generator. The time

constant may be changed at any time, but the new

value does not take effect until the next time the time

constant is loaded into the down counter. It is re-

commended that the BRG be disabled before wri-

ting to this register, as no attempt was made to

synchronize the loading of a new time constant with

the clock used to drive the BRG. This register is re-

set to ”00H” by a channel or hardware reset.

BAUD RATE GENERATOR CONTROL RE-

GISTER (BRGCTL)

This register contains the control bits used to pro-

gram the baud rate generator and to select the BRG

output mode. This register is reset to ”00H” by a

channel or hardware reset.

D7, D6, D5, D4 : Not Used (read as zeros)

D3 : Receiver Clock, Internal/External

This bit determines the direction of the RxC pin.

When this bit is set to a one, the RxC pin is the output

of the baud rate generator. If this bit is a zero, the

RxC pin is an input, and an external source must

supply the receiver clock. The receiver clock is al-

ways the signal on the RxC pin, except in Loop

Mode, when the transmitter clock is connected inter-

nally to the receiver clock.

D2 : Transmitter Clock, Internal/External

This bit determines the direction of the TxC pin.

When this bit is set to a one, the TxC pin is the output

of the baud rate generator. If this bit is a zero, the

TxC pin is an input, and an external source must

supply the transmitter clock. The transmit clock is al-

ways the signal on the TxC pin.

D1 : Divide By 64/4

This bit specifies the minimum BRG input clock cy-

cles to output clock cycle. This minimum occurs

when the Time Constant Register is loaded with a

”01H” value. When this bit is set to a one, 64 input

clocks are required for every output clock. When this

bit is a zero, four input clocks are required for every

output clock.

D0 : Baud Rate Generator Enable

This bit controls the operation of the baud rate gene-

rator. When this bit is set to a one, the BRG will start

counting down from the value left in the down coun-

ter when this bit was last reset to zero. If the Time

Constant Register is loaded while this bit is reset, the

new time constant value is loaded immediately into

the down counter. The baud rate generator is disa-

bled from counting when this bit is reset.

INTERRUPT VECTOR REGISTER

(VECTRG)

This register is used to hold a vector that is passed

to the CPU during an interrupt acknowledge cycle.

This register can also be accessed through a

read/write cycle. If the Status Affects Vector bit in the

Interrupt Control Register is disabled, the value pro-

grammed into the Vector Register will be passed to

the CPU during an interrupt acknowledge cycle or

a read cycle. If the Status Affects Vector bit in either

channel is enabled, the lower three bits of this regis-

ter are modified, according to the table listed in the

Interrupt Control Register description. With Status

Affects Vector on, and no interrupt pending in the

SIO, the lower three bits will be read as 011. Only

e Vector Register exists in the SIO, but it can be ac-

D 0

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

D7 D6 D5 D4

D 3

D 2

RxC

INT/EXT

TxC

INT/EXT

DIVIDE

BY 64/4

BRG

ENABLE

D 5

* Variable if Status Affects Vectors is Enabled.

MK68564

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